39results about How to "Large data storage capacity" patented technology

The security clearance card, system, and method include a card that stores data to verify the identity of an owner of the card. In addition to other types of information, the card stores biometric data of the owner and other identity data. Different portions of the data may be encrypted with different encryption techniques based upon a predetermined level of security assigned to the portions of the stored data. Reader elements are then capable of reading at least a portion of the encrypted data stored on the security clearance card, and receiving at least one biometric from an individual. The biometric stored in the card is then compared with the biometric of the individual presenting the security clearance card to verify that the holder of the card is the owner of the card.

The security clearance card, system and method of the present invention includes a card that stores data to verify the identity of an owner of the card. In addition to other types of information, the card stores biometric data of the owner and other identity data. Different portions of the data may be encrypted with different encryption techniques based upon a predetermined level of security assigned to the portions of the stored data. Reader elements are then capable of reading at least a portion of the encrypted data stored on the security clearance card, and receiving at least one biometric from an individual. The biometric stored in the card is then compared with the biometric of the individual presenting the security clearance card to verify that the holder of the card is the owner of the card.

A semiconductor device with an improved arithmetic processing speed and a decreased circuit size, and its driving method are provided. In the semiconductor device, a first terminal of a first transistor and a gate of a second transistor are electrically connected to a first terminal of a capacitor, and a control circuit is electrically connected to a second terminal of the capacitor. The control circuit supplies a first potential to the second terminal of the capacitor, in other words, adds a value corresponding to the first potential to the value of first data previously retained in the gate of the second transistor in order to obtain second data. In the second transistor, the second data, specifically, a third potential commensurate with the potential of the gate will be output from a second terminal when a second potential is supplied to a first terminal.

Optimum relationship of data between local features, a coding data quantity, a quantity that expresses picture quality, and local coding parameters, for each block is stored. Extracted local features of one to a plurality of frames are stored. Setting of local coding parameters of each block included in one to a plurality of frames is adjusted so that the distribution of coding data quantity of each block in one to a plurality of frames is optimized within a predetermined range of data quantity based on the stored optimum relationship and local features.

Proposed is an action machine for processing packet data in a network processor. The action machine comprises: first and second data storage units adapted to store data for processing; and a processing unit adapted to process data from the first and second data storage units. The first storage unit is adapted to be accessed by the processing unit and a unit external to the action machine, and the second storage unit is adapted to only be accessed by the processing unit.

The invention discloses an active passive type double-frequency chip and an RFID system. The active passive type double-frequency chip comprises a passive awakening module and an active module, wherein the passive awakening module is used for receiving 125 K low-frequency activation signals, the active module is used for transmitting 2.4 G radio frequency signals, the passive awakening module comprises a first radio frequency antenna, a rectifying circuit, a demodulation circuit, a logic circuit and a power supply switch which are sequentially and electrically connected, the input end of the power supply switch receives awakening signals transmitted by the logic circuit and receives awakening feedback signals of the active module, the output end of the power supply switch is electrically connected with the awakening enabling end of a microprocessor circuit, and the output end of the microprocessor circuit is electrically connected with a second radio frequency antenna used for transmitting 2.4 G radio frequency signals. The active module is in the electricity-saving mode when the active passive type double-frequency chip is in the normal state, and therefore electricity is saved; when the 125 K low-frequency activation signals are received, the passive awakening module can awaken the active module, and the active module can transmit the 2.4 G radio frequency signals; thus, the active passive type double-frequency chip has the advantages of being large in data storage capacity, long in reading-writing distance and long in service life at the same time.

A dual processor electronic parking meter (EPM) accepts a plurality of ISO compliant smart cards and authorizes payment of purchased time. The EPM of the invention is equipped with a card reader module (CRM) which accepts / validates transactions effected on smart cards, and also accepts a interface card for connection to a data terminal for revenue collection, meter configuration and meter firmware maintenance. The EPM includes a multi-lingual, intelligent, mixed-mode graphics and icon based display with greater visibility. When the EPM is idle, various sections of EPM are in a sleep mode for prolonging the life of the batteries. The EPM wakes up whenever a card is in the CRM, a coin is inserted, or a key for selecting the parking time and the type of operation is actuated. The EPM contains a large memory and can be reprogrammed in the field to support new cards, different user languages, and system parameters etc.