31 results about "High performance design" patented technology

A method, system and program are provided for dynamically reconfiguring a pipelined processor to operate with reduced power consumption without reducing existing performance. By monitoring or detecting the performance of individual units or stages in the processor as they execute a given workload, each stage may use high-performance circuitry until such time as a drop in the throughput performance is detected, at which point the stages are reconfigured to use lower-performance circuitry so as to meet the reduced performance throughput requirements using less power. By configuring the processor to back off from high-performance designs to low-performance designs to meet the detected performance characteristics of the executing workload warrant, power dissipation may be optimized.

A method, system, computer system, and computer program product including an algorithm that performs the constraints-based global routing step in the physical design of integrated circuits. The algorithm is based on finding routes for the entire circuit based on constraints being satisfied for the entire design. Initially, for each net, a set of possible routing solutions is determined based on applicable constraints. The possible solutions for the nets are combined to create a highly-connected “intersection graph,” with each intersection graph node representing a net. The intersection graph is partitioned based on constraints and performance criteria. An optimal solution is determined for each partition. The optimal solutions for the partitions are then combined to produce a global routing solution. The global routing solution is provided to a detailed router, which completes the routing for the design.

Power, routability and electromigration have become crucial issues in modem microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance on the clock nets can help reduce clock power, however, it may hurt performance due to some loss of flexibility in physically placing those components. The present invention provides techniques to optimally place clock components in a regular fashion so as to minimize clock power within a performance constraint. A rectangular grid is created and clock distribution structures are assigned to the grid intersection points. Latches are then located around the clock distribution structures to minimize an overall distance for connections between the latches and respective clock distribution structures. The horizontal and vertical pitches of the grid may be independently adjusted to achieve a more uniform spread of the clock distribution structures.

Power, routability and electromigration have become crucial issues in modem microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance of the clock nets can help reduce clock power, however, it may hurt performance due to some loss of flexibility in physically placing those components. The present invention provides techniques to optimally design a clock network by logically assigning clusters of the latches to respective clock distribution structures, placing clock pins at favored pin locations, and placing clock distribution structures directly underneath the clock pins. The clock distribution structures may be moved to favored distribution locations along the clock stripes, and new optimal clustering generated between the latches and the clock distribution structures. These three optimizations are preferably repeated iteratively to derive a local optimal solution for the clock network.

Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be reported in real time, while the user is manually editing the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, and scanning in the direction of the edge orientations. Scans stop only at corner positions and populate the layout topology database with what information can be gleaned based on the current scan line. The different scans need not reach each corner simultaneously.

One embodiment of the present invention sets forth a twelve transistor static random access memory storage cell that provides two write ports and three read ports. The write word line operates at twice the clock frequency. The write bit lines are differential to provide high-performance writes. Each read word line operates at the clock frequency. Single-ended read bit lines are used to provide read performance comparable to write performance. The resulting storage cell only requires four horizontal word lines and five vertical bit lines, enabling very dense, yet high-performance designs.

A latch placement tool determines a shape for a cluster of latches from a preliminary layout (or based on a netlist), including an aspect ratio of the shape, and generates a template for placement of the latches in conformity with the shape. Latches are placed around a local clock buffer (LCB) based on latch size, from largest latch first to smallest latch last, and based on their ideal locations given the target aspect ratio. The ideal locations may be further based on the clock driver pin configuration of the LCB. The final template preferably has an aspect ratio that is approximately equal to the aspect ratio of the shape of the cluster, but the latch placement may be constrained by clock routing topology. Latch placement within a cluster can be further optimized by swapping one of the latches with another to minimize total wirelength of the design.

Power, routability and electromigration have become crucial issues in modern microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance on the clock nets can help reduce clock power, however, it may hurt performance due to some loss of flexibility in physically placing those components. The present invention provides techniques to optimally place clock components in a regular fashion so as to minimize clock power within a performance constraint. A rectangular grid is created and clock distribution structures are assigned to the grid intersection points. Latches are then located around the clock distribution structures to minimize an overall distance for connections between the latches and respective clock distribution structures. The horizontal and vertical pitches of the grid may be independently adjusted to achieve a more uniform spread of the clock distribution structures.

The present invention discloses a multi-turn absolute value encoder, comprising: a detection module, a power supply working module and a power-off working module; the detection module is used for performing power-on detection and power-off detection; when the power-on is detected, the power supply working module works; when the power-off is detected, the power-off working module works; the power working module includes a single-turn absolute value encoder and a single-chip microcomputer, the single-chip microcomputer collects rotor position information of a motor via the single-turn absolute encoder; the power-off working module includes a common encoder and a low-power single-chip microcomputer, and the low-power microcomputer collects the rotor position information of the motor through the common encoder. The multi-turn absolute value encoder with low-cost high-performance design combines advanced algorithms, to achieve low cost, high precision, small size and unlimited measurement range is unlimited, and achieves continuous long-term use without external power supply. The invention also discloses a working method of a multi-turn absolute value encoder.

A method, system and program are provided for dynamically reconfiguring a pipelined processor to operate with reduced power consumption without reducing existing performance. By monitoring or detecting the performance of individual units or stages in the processor as they execute a given workload, each stage may use high-performance circuitry until such time as a drop in the throughput performance is detected, at which point the stages are reconfigured to use lower-performance circuitry so as to meet the reduced performance throughput requirements using less power. By configuring the processor to back off from high-performance designs to low-performance designs to meet the detected performance characteristics of the executing workload warrant, power dissipation may be optimized.

A latch placement tool determines a shape for a cluster of latches from a preliminary layout (or based on a netlist), including an aspect ratio of the shape, and generates a template for placement of the latches in conformity with the shape. Latches are placed around a local clock buffer (LCB) based on latch size, from largest latch first to smallest latch last, and based on their ideal locations given the target aspect ratio. The ideal locations may be further based on the clock driver pin configuration of the LCB. The final template preferably has an aspect ratio that is approximately equal to the aspect ratio of the shape of the cluster, but the latch placement may be constrained by clock routing topology. Latch placement within a cluster can be further optimized by swapping one of the latches with another to minimize total wirelength of the design.

The present invention includes, from an object side to an image-plane side: an aperture stop with a predetermined diameter, a first lens with a positive refractive power having a convex surface on the object side, a second lens with a positive refractive power having a concave surface on the object side, and a third lens with a negative refractive power having a convex surface on the object side. The second and third lenses have aspherical surfaces on their object-side and image-plane-side surfaces. The third lens is formed with an inflection point where the curvature orientation changes within the effective diameter range of the aspherical surface on the image-plane side. An appropriate back focus is maintained while the total length of the lens system is reduced. A compact, thin, high-performance design is achieved, which effectively corrects various aberrations, especially astigmatism and distortion, and is suited for digital cameras using high-density solid-state imaging elements of one million pixels or more.

Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be reported in real time, while the user is manually editing the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, and scanning in the direction of the edge orientations. Scans stop only at corner positions and populate the layout topology database with what information can be gleaned based on the current scan line. The different scans need not reach each corner simultaneously.

A compact monochrome ink jet printhead having a staggered high-density arrangement of ink drop generators for high-performance printing. The present invention provides a high-performance design that enable high-resolution and high-speed printing while reducing cost due to an efficient use of printhead space. In particular, the compact, high-performance printhead of the present invention includes several thermally-efficient aspects that allow a large number of ink drop generators to be placed on a compact printhead while minimizing problems such as thermal excursions. In a preferred embodiment, the ink drop generator density on the compact printhead exceeds 10 ink drop generators per square millimeter and the compact printhead contains at least 350 nozzles. The ink drop generators are arranged in at least four parallel rows. Each row is staggered (or offset) relative to an adjacent row to provide a greater effective pitch that a non-staggered arrangement.

Roughly described, a design rule data set is developed offline from the design rules of a target fabrication process. A design rule checking method involves traversing the corners of shapes in a layout region, and for each corner, populating a layout topology database with values that depend on respective corner locations. After the layout topology database is populated, the values are compared to values in the design rule data set to detect any design rule violations. Violations can be reported in real time, while the user is manually editing the layout. Preferably corner traversal is performed using scan lines oriented perpendicularly to edge orientations, and scanning in the direction of the edge orientations. Scans stop only at corner positions and populate the layout topology database with what information can be gleaned based on the current scan line. The different scans need not reach each corner simultaneously.

Techniques are disclosed for designing manufacturing facilities. A design application imports a computer-aided design (CAD) model and metadata associated with a manufacturing facility to generate a data set that specifies geometric and manufacturing constraints of the manufacturing facility. The design application performs optimization operations based on the data set to identify one or more high-performing designs that assign components to docks in the manufacturing facility. The optimization operations can include genetic optimization operations that generate multiple generations of designs, each of which is evaluated based on a travel distance, congestion, and number of turns associated with paths traversed by components for the design.

The invention discloses a design and machining method of an automobile closed section structural member with multiple cavities and variable wall thickness, and belongs to the technical field of forming. The closed cross section structural member adopts at least two pipe fittings which are combined and fixedly connected in a mechanical connection mode to form a closed cross section with two or more internal cavities; the structural member is made of a variable-thickness steel material for rolling and hot stamping, and different pipe fittings forming the closed-section structural member have variable-wall-thickness design and the same bending curvature in the length direction of the part; at least three equal-thickness intervals are included, and thickness transition sections are arranged between the equal-thickness intervals; machining and forming are carried out by adopting an online induction quenching strengthening process; different pipe fittings forming the closed-section structural member can be differentiated and modularly designed in the aspects of section thickness and section shape according to design and functions, and high-performance design and low-cost manufacturing of the closed-section structural member are achieved. The invention can be widely applied to the field of design and processing of various closed-section structural members.

The present invention includes, from an object side to an image-plane side: an aperture stop with a predetermined diameter, a first lens with a positive refractive power having a convex surface on the object side, a second lens with a positive refractive power having a concave surface on the object side, and a third lens with a negative refractive power having a convex surface on the object side. The second and third lenses have aspherical surfaces on their object-side and image-plane-side surfaces. The third lens is formed with an inflection point where the curvature orientation changes within the effective diameter range of the aspherical surface on the image-plane side. An appropriate back focus is maintained while the total length of the lens system is reduced. A compact, thin, high-performance design is achieved, which effectively corrects various aberrations, especially astigmatism and distortion, and is suited for digital cameras using high-density solid-state imaging elements of one million pixels or more.

A high performance design architecture for network function virtualization is an efficient network function virtualization framework which eliminates the processing redundancy in network functions byaggregating the operations of the network functions in a service chain on a data stream, so as to realize an efficient network data path. According to the design architecture, a local action matchingtable is established in each network function to record the operation behaviors on the data packets in the data stream and the states of the network functions, and a global action matching table is established to aggregate all the local action matching tables. Meanwhile, an event triggering table and a new data packet processing mode are used to guarantee the logical correctness of the network functions at run time, and the performance of the system is improved through the parallelization of network function functions. The processing delay and throughput of the network function service chain are significantly optimized under the condition of guaranteeing the logical correctness of the network functions.

The invention provides an amplifier circuit, which is composed of a first capacitor, a first transistor, a second transistor, a first resistor, a current source and a load. The first transistor is connected to the gate of the second transistor and is coupled to the signal input terminal. Both the first transistor and the source of the first transistor are grounded; the drain of the second transistor is connected to one end of the load and is also coupled to the signal output end. The drain of the first transistor is connected to the output of the current source, the gate of the first transistor through a first resistor, and the drain of the second transistor through a first capacitor. Through the technical proposal of the invention, the multiplexing of the bias current and the bias transistor in the amplification circuit is realized, the current use efficiency can reach 100% of the theory, and the low power consumption, low current and high performance design can be achieved to a greater extent.

The invention belongs to the technical field of materials, and especially relates to a composite material and a preparation method thereof. The polypropylene composite material with high performance designed by the invention consists of the following raw materials, by weight: 45%-55% of a PP homopolymer component, 10%-20% of a PP copolymer component, 3%-8% of a reactive compatibilizer, 16%-40% ofalkali-free glass fibers, 0.1%-0.5% of an anti-hydrolysis agent, 0.2%-0.8% of an antioxidant, and 0.1%-0.5% of other auxiliary agents. According to the preparation method, the PP homopolymer componentis added to improve the rigidity of the material, a part of specially selected PP copolymer is added to improve a part of the toughness, and a very high performance balance can be achieved through the combination of the selected glass fibers. The addition of the anti-hydrolysis agent and the long-term antioxidant can keep the physical properties of the material unchanged for a long time.

Techniques are disclosed for designing manufacturing facilities. A design application imports a computer-aided design (CAD) model and metadata associated with a manufacturing facility to generate a data set that specifies geometric and manufacturing constraints of the manufacturing facility. The design application performs optimization operations based on the data set to identify one or more high-performing designs that assign components to docks in the manufacturing facility. The optimization operations can include genetic optimization operations that generate multiple generations of designs, each of which is evaluated based on a travel distance, congestion, and number of turns associated with paths traversed by components for the design.

The invention discloses a power-driven hydraulic hydrology tour gauging car which comprises a car body. A vehicle-mounted storage battery and a hydrology tour gauging device are arranged on the car body and electrically connected. By means of the technical scheme, compared with the prior art, a power unit is transferred into a hydrographic winch, a cable is led out from the vehicle-mounted storage battery to be connected with the power unit, a power generating system of the car is used for driving the power unit to provide a hydraulic power source for the hydrology tour gauging car, pressure loss is little, overall disassembly and maintenance is facilitated due to the compact structure, and reliability is high; the power unit can work intermittently according to the needs of actions of the hydrographic winch, so that environment protection and energy conservation are achieved, oil temperature is prevented from being too high, and the high-performance design requirement of the tour gauging car is met. The power-driven hydraulic hydrology tour gauging car solves the problems that power is shared by all car types, connecting pipelines of the winch and the car are too many, the winch is not easy to disassemble, and the temperature of hydraulic oil is too high due to long-time continuous flow gauging.

The invention provides a three-way catalytic converter, an engine exhaust assembly and an automobile. By adopting an intake flange with blades and an intake pipe matched with it, the intake end of the three-way catalytic converter is analyzed from the overall structure. The optimization can not only solve the problem that the intake pipe and the three-way catalytic converter casing cannot be welded and matched due to the smaller layout space of the three-way catalytic converter, but also can improve the uniformity coefficient of the airflow and meet the high-performance design requirements.

The present invention discloses a multi-turn absolute value encoder, comprising: a detection module, a power supply working module and a power-off working module; the detection module is used for performing power-on detection and power-off detection; when the power-on is detected, the power supply working module works; when the power-off is detected, the power-off working module works; the power working module includes a single-turn absolute value encoder and a single-chip microcomputer, the single-chip microcomputer collects rotor position information of a motor via the single-turn absolute encoder; the power-off working module includes a common encoder and a low-power single-chip microcomputer, and the low-power microcomputer collects the rotor position information of the motor through the common encoder. The multi-turn absolute value encoder with low-cost high-performance design combines advanced algorithms, to achieve low cost, high precision, small size and unlimited measurement range is unlimited, and achieves continuous long-term use without external power supply. The invention also discloses a working method of a multi-turn absolute value encoder.

Techniques are disclosed for designing manufacturing facilities. A design application imports a computer-aided design (CAD) model and metadata associated with a manufacturing facility to generate a data set that specifies geometric and manufacturing constraints of the manufacturing facility. The design application performs optimization operations based on the data set to identify one or more high-performing designs that assign components to docks in the manufacturing facility. The optimization operations can include genetic optimization operations that generate multiple generations of designs, each of which is evaluated based on a travel distance, congestion, and number of turns associated with paths traversed by components for the design.

The invention discloses a mini-fan performance test system based on a human-computer interaction interface. The human-computer control and display module of the test system is connected with a drive motor module, a performance parameter data acquisition module and a pulling motor module respectively; the human-computer control and display module contains a communication interface, a controller and the human-computer interaction interface; and the human-computer control and display module obtains the instructions of the user through the human-computer interaction interface, then the instructions are processed by the controller to control the rotation speed of the drive motor module and the frequency of the pulling motor module through the communication interface, and the human-computer control and display module exchanges data with the performance parameter data acquisition module to obtain the required information. The test system of the invention is suitable for the performance testsof various mini-fans; the main performance parameters to be tested contain static pressure, flow, rotation speed, torque, wind speed and the like. The invention provides real data for the high-performance design of the mini-fan and plays an important role in the optimization of the structure and parameters of the mini-fan.

The invention provides a three-way catalyst, an engine exhaust assembly and an automobile. According to the three-way catalyst, the engine exhaust assembly and the automobile, the air inlet end of thethree-way catalyst is optimized from the overall structure by adopting an air inlet flange with blades and an air inlet pipeline matched with the air inlet flange, the problem that an air inlet pipeline and a three-way catalyst shell cannot be welded and matched with each other due to the fact that the arrangement space of a three-way catalyst becomes small can be solved, in addition, the uniformity coefficient of airflow can be increased, and the high-performance design requirement is met.