55 results about "Tensor processing unit" patented technology

A personalized diagnostic system for healthcare, comprehensive: a deep learning framework trained on a diverse dataset of medical images to analyze and interpret medical images; a data fusion module that integrates imaging data with non-imaging patient data such as electronic health records (EHRs), genetic information, and biomarker profiles; a high-performance computing system that uses GPUs (Graphics Processing Units) and TPUs (Tensor Processing Units) for real-time and batch processing of medical data; an intuitive user interface that displays diagnostic results, visualizations of medical images, and interactive functions for adjusting diagnostic parameters; a continuous learning mechanism that updates the deep learning models based on new data and expert feedback; a cloud-based platform for managing the continuous learning process, including the storage of anonymized patient data and diagnostic results; an explanatory module that provides detailed explanations of the diagnostic process using techniques such as Grad-CAM (Gradient-weighted Class Activation Mapping) and SHAP (SHapley Additive exPlanations); and a role-based access control (RBAC) mechanism to secure patient data.

A system for AI-supported cybersecurity and regulatory compliance in energy distribution networks, consisting of: a hardware-embedded data acquisition module configured to intercept, capture, and time-stamp operational data streams and to control data traffic from SCADA (Supervisory Control and Data Acquisition) systems, AMI (Advanced Metering Infrastructure) systems, and energy management systems (EMS) via multiple communication protocols without operational latency; an FPGA-based deep packet inspection unit coupled with the data acquisition module, wherein the FPGA firmware is configured to perform line rate filtering, protocol decomposition and metadata extraction of the acquired data and forwards preprocessed packet data to an AI processing unit; an AI processing unit consisting of a multi-core central processing unit (CPU), a dedicated AI accelerator selected from a graphics processing unit (GPU) or a tensor processing unit (TPU), and a volatile memory buffer; a response orchestration module that is communicatively coupled with network management devices and operations controllers, wherein the response orchestration module is configured to perform automated security and compliance remediation measures, including network isolation of compromised segments, enforcement of protocol encryption, and privilege revocation; and an immutable audit logging subsystem configured to record all detected events, compliance assessments, and corrective actions in a blockchain-based distributed ledger, with each log entry cryptographically anchored with a secure hash value and digitally signed with keys stored in a secure hardware enclave.

An integrated circuit (IC) layer stack is disclosed that integrates bypass chiplets in the IC layer stack without requiring fabrication of through-silicon vias (TSV) in a digital device for signals and power to a memory stack located above the digital device. Not requiring adding TSVs to an existing design high-performance digital device significantly reduces and / or eliminates digital device modification costs and time to manufacture new products consisting of three-dimensional stacked memory and digital device organizations. The bypass chiplets may be passive with just through conductors in silicon, or active with logic circuits therein. Flexibility of placement of the bypass chiplets in the IC layer stack in combination with an active interposer provides for many possible configurations of IC layer stacks. The digital device may be a microcontroller, a microprocessor, a PLA, an ASIC, a DSP, a GPU, a FPGA, neural processing unit, tensor processing unit, or any combination thereof.

The invention provides a generation method of a sub-flow type sparse convolution rule table and a convolution operation method and device, and provides the generation method of the sub-flow type sparse convolution rule table for realizing sub-flow type sparse convolution on a tensor processing unit, and the generation method comprises the steps: calculating the offset of an input coordinate; calculating corresponding output coordinates of the input coordinates in each filter kernel, and calculating the offset of the output coordinates; the offset of the input coordinates and the offset of the output coordinates corresponding to the filter core are compared, a sequence mask corresponding to the filter core is obtained, and elements, not equal to 0, in the sequence mask indicate that the offset of the corresponding set of input coordinates is the same as the offset of the corresponding set of output coordinates; and obtaining a rule table corresponding to the filter core based on the sequence mask corresponding to the filter core and a mask screening function, and performing substream sparse convolution operation based on the rule table. The number of times of data access is effectively reduced, and the operation efficiency is improved.

A mobile edge computing system, a communication network and a method of using a mobile edge computing device. The mobile edge computing system includes a communication module that establishes signal communication over numerous wireless communication protocols at least one of which uses a low power wide area network protocol. A logic device is made up of a distributed set of processing units including both a central processing unit and one or more processors configured for performing machine learning operations the latter of which include one or more of a graphical processor unit and a tensor processing unit. When the system receives event data that has been acquired by one or more of the communication module and a sensor, the system executes a trained machine learning model and conveys, using the low power wide area network protocol, an output that has been produced by the trained machine learning model.

The invention discloses an accelerator supporting an attention mechanism, which is used for realizing matrix multiplication operation, scaling operation or nonlinear activation processing related to the attention mechanism, and is characterized in that a weight cache state machine module is used for controlling weight data to flow from a system bus to a weight cache unit; the thread cache state machine module is used for controlling thread data to flow from the system bus to the thread cache unit; the attention tensor processing unit state machine module is used for controlling loading and flowing of thread data and weight data from the two-dimensional systolic array in different directions, the thread data is controlled to be transmitted to the next processing unit in each period, and the weight data is spread to the processing units in the corresponding directions in a broadcast mode; the calculation result of the two-dimensional systolic array is transmitted to different branches according to whether nonlinear activation processing needs to be executed or not. According to the method, data filling is carried out on the matrix so that the matrix can be matched with the systolic array data stream, and then the attention mechanism with the variable sequence length is accelerated through hardware.

Various examples are provided related to side-channel awareness. In one example, a method for side-channel awareness training includes generating trained models by stochastically training neural network models using a common training dataset; generating an inference model based upon random selection of parameters from one or more of the trained models; and training the inference model with the selected parameters. The trained inference model can be executed on an edge Tensor Processing Unit (TPU). The models can be trained offline. An input signal can be processed using the trained inference model to generate an output signal for transmission.

A cloud-integrated, AI-powered smart speaker for language learning, which includes the following: A microphone array for speech capture; ◯ an on-device AI module with a Neural Processing Unit (NPU) or Tensor Processing Unit (TPU) for real-time speech analysis; • Wi-Fi and 5G connectivity for secure data synchronization with cloud servers; ◯ a cloud-based AI engine that uses serverless computing services to trigger AI models for advanced language assessment and adaptive learning; ◯ a cloud storage system with relational databases for structured data, such as user profiles and progress metrics, and object storage for unstructured data, such as audio recordings, secured with AES-256 encryption and RBAC for data protection; ◯ a true-to-life speaker for AI-generated speech output; ◯ a screen (OLED / E-Ink) for text corrections and real-time lesson guidance; ◯ Touch and gesture sensors for user interaction; ◯ A battery module with USB-C charging function for portability.

The present application relates to the technical field of data processing, and is used for realizing universal and efficient processing of a multi-dimensional tensor. Provided are a processor, a tensor processing method, and a device. A tensor processing unit in the processor comprises: a preprocessing circuit, which is used for adjusting first dimension information of a multi-dimensional tensor, so as to obtain second dimension information, wherein the product of the size of any dimension in the second dimension information and the capacity of a unit access storage space is smaller than or equal to the capacity of a data cache; an address generation circuit, which is used for generating, on the basis of the second dimension information, a plurality of source addresses corresponding to a plurality of pieces of data in the multi-dimensional tensor; an access control circuit, which is used for determining a plurality of pieces of cache mapping information corresponding to the plurality of source addresses, and sending a plurality of access requests on the basis of the plurality of source addresses, and is used for acquiring from a first memory the plurality of pieces of data of the multi-dimensional tensor; and the data cache, which is used for caching the plurality of pieces of data on the basis of the plurality of pieces of cache mapping information.

The invention relates to the field of tensor processing, and provides a tensor dimension recombination method and device for a tensor processing unit, and a chip. The method comprises the following steps: checking whether the total number of elements of an input tensor is equal to that of elements of a target output tensor; based on the shape parameters of the input tensor and the target output tensor, storage layout information and hardware architecture characteristics of a tensor processing unit, performing mode judgment on the current dimension recombination operation to judge whether the current dimension recombination operation is matched with a preset high-frequency special judgment mode or not; when the current dimension recombination operation is matched with the high-frequency special judgment mode, a hardware acceleration execution mode corresponding to the high-frequency special judgment mode is adopted, and tensor dimension recombination is completed in an on-chip storage range; when the current dimension recombination operation is not matched with the high-frequency special judgment mode, tensor dimension recombination is completed through parallel computing and cooperative processing in a general recombination execution mode oriented to a hierarchical storage structure. The respe execution efficiency can be improved, occupation of on-chip memory resources is reduced, and waste of bandwidth resources is avoided.

The invention provides a tensor calculation acceleration method and device and electronic equipment, and belongs to the technical field of artificial intelligence, and the method comprises the steps: generating the scheduling information of a tensor calculation task through a scheduling kernel according to a task dependency graph issued by a host, and determining the control information and tensor data corresponding to the tensor calculation task based on the scheduling information; packaging the control information and the tensor data into a message, and injecting the message into a multi-link network on chip; transmitting the message to a tensor processing unit node specified by the scheduling information through a multi-link network-on-chip; executing a corresponding tensor calculation task on the control information in the message through a tensor processing unit node to generate a calculation result; and transmitting a calculation result back to the host. According to the method, a control flow and data flow separation scheduling mechanism based on the multi-link network-on-chip is constructed, so that the overall performance of tensor calculation is improved in the face of a large-scale tensor calculation task.

Disclosed in the embodiments of the present application are a processor, a computing node, and a computing cluster, which are used for simplifying the network architecture of the computing cluster. The processor comprises: a general-purpose protocol port, which is used for supporting a first communication protocol and a second communication protocol, wherein the second communication protocol is different from the first communication protocol; the first communication protocol is a communication protocol of a first network, the second communication protocol is a communication protocol of a second network, the first network is used for supporting communication between a plurality of processors in one computing node including the processor, the second network is used for supporting communication between the processor and other processors comprised in other computing nodes, and the processor is any one of a graphics processing unit (GPU), a tensor processing unit (TPU), a neural processing unit (NPU) and a general-purpose graphics processing unit (GPGPU).

A computing device includes at least one processor, one or more non-transitory computer-readable storage media, a system for fine-tuning a large language model under low-bit weight-activation quantization. The computing device further comprises a graphics processing unit (GPU), a neural processing unit (NPU), or a tensor processing unit (TPU). The hardware interface module of the system is configured to load a low-bit model representation from the memory module and transmit the model representation to the GPU, NPU, or TPU for inference execution.

Disclosed in the present application is a tensor processing unit. The tensor processing unit comprises: an instruction sequence module, which is configured to generate a first instruction sequence and / or a second instruction sequence on the basis of a tensor operation instruction and preset configuration information, wherein the first instruction sequence comprises a plurality of first operation instructions, the second instruction sequence comprises a plurality of second operation instructions, and the preset configuration information comprises first configuration information and / or second configuration information; a data loading module, which is configured to sequentially load, on the basis of the first instruction sequence or the second instruction sequence, into corresponding registers data to be operated; a first computing module, which is configured to sequentially read, on the basis of the first instruction sequence, data from the registers, so as to perform in-memory computing; and a second computing module, which is configured to sequentially read, on the basis of the second instruction sequence, data from the registers, so as to perform non-in-memory computing. Further provided in the present application is a tensor processing method. A unified macro instruction is used to call different computing modules for in-memory computing or non-in-memory computing, thereby reducing the programming complexity and improving the computing efficiency.

Systems and methods for high-bandwidth, minimally invasive brain-computer interfaces (BCIs) are disclosed. The BCIs are configured for deployment and operation in conjunction with a comprehensive interventional electrophysiology procedural suite. Three primary methods of minimally invasive electrode array delivery are disclosed: (1) cortical surface delivery, (2) ventricular delivery, and (3) endovascular delivery. Additionally, systems and methods for interacting with such high-bandwidth electrode arrays are discussed, including real-time imaging, signal processing, and neural decoding. Systems and methods for architectures for accelerating the underlying computational processes (such as graphics processing units or tensor processing units) are also discussed. Multiple applications of BCIs are discussed, with emphasis on restoration, rehabilitation, and augmentation of neurologic function.

The application relates to the technical field of data processing, and particularly discloses a TPU instruction addressing mapping method and device based on a base register. When a tensor processing unit (TPU) instruction is received, a data processing requirement is acquired. When the data processing requirement is data non-aggregation, an address allocation strategy is determined based on the number of base registers and the sum of the data quantity of model input data and model output data. Each data is allocated a compiler address based on the base registers and the address allocation strategy. During TPU runtime, the compiler address is parsed to obtain the physical address of each data, and each data is transmitted according to the physical address. According to the application, each data is allocated an address based on the base register, the physical address of each data can be obtained according to different base registers, and then the data in the TPU device memory can be directly read without copying the data in the TPU device memory to the operation space, so that the data acquisition efficiency is improved, and the model inference efficiency is improved.

A system for automated, middleware-based intelligent data mapping between heterogeneous enterprise resource planning (ERP) systems and cloud platforms, the system comprising the following: an ERP data acquisition unit with a variety of physical communication ports, selected from Ethernet and serial ports, a network interface controller physically connected to the communication ports, and a DMA (Direct Memory Access) controller configured to transfer raw ERP data packets into a volatile buffer memory without processor intervention; a Semantic Mapping Unit consisting of a Field Programmable Gate Array (FPGA) configured as a lexical analyzer to analyze ERP schema definitions and extract entity descriptors, and a Tensor Processing Unit (TPU) configured to evaluate the semantic similarity between heterogeneous schema elements based on ontological models stored in a non-volatile memory repository; a transformation logic unit comprising a parallelized vector processor configured to perform matrix-based transformations, field normalizations and structural reorganization of ERP data into a harmonized format, and a rule application circuit configured to perform compliance-based anonymization, unit conversions and value scaling prior to cloud distribution; a cloud interface unit comprising a protocol adapter bank with encoders, translators, and message queue writers, wherein the cloud interface unit is coupled with a cryptographic controller configured with a hardware public key infrastructure (PKI) circuit to generate digital signatures and verify integrity codes for all outgoing payloads; and a Feedback Learning Control Unit implemented in the firmware, wherein the engine is electrically coupled to the Semantic Mapping Unit and the Transformation Logic Unit and is configured to monitor error logs, success rates and acknowledgment codes received from the cloud platforms and to update the semantic and transformation rules stored in the non-volatile memory repository accordingly.

The present disclosure relates to a data processing method of a tensor processing unit (TPU), comprising: obtaining a time for a first functional unit in the tensor processing unit (TPU) to perform a predetermined operation; determining a reference time for the first functional unit and / or a second functional unit in the tensor processing unit (TPU) to run according to the time for the first functional unit to perform the predetermined operation, wherein the reference time comprises a start time and / or an end time of data processing; and associating data processed by the first functional unit and / or the second functional unit based on the reference time. In this way, the association between the data processed by different functional units is established by the reference time, the data is associated and integrated, and the efficiency and accuracy of data analysis are improved compared with the way of finding relevance based on manual association of data.

The invention discloses an internet resource long-term storage management and storage system, which comprises a space-time coding layer which is based on an FPGA (Field Programmable Gate Array) main control chip, comprises a parallelized tensor processing unit and is used for converting digital resources and metadata and context relationships thereof into a space-time coding body with a time self-description capability; the storage unit is used for receiving the space-time coding body from the space-time coding layer and permanently solidifying the space-time coding body in a tamper-resistant physical form; and the four-dimensional continuation control layer is used for dynamically managing the integrity, readability and authenticity of resources in the whole life cycle through an autonomous evolution algorithm and a distributed verification network. Through collaborative innovation of a space-time coding body (an information layer), a holographic cold memory (a physical layer) and a continuation control network (a management and control layer), the basic challenges of long-term storage of Internet resources in the aspects of authenticity, integrity, availability, safety, cost, technical dependence and the like are systematically handled.

Provided in the embodiments of the present disclosure are a tensor data transformation method, a tensor processing unit, a processor, a system on a chip, and a computing device. The tensor processing unit comprises: a register array unit, which comprises at least a source address register, a destination address register, and a source tensor parameter register; an instruction decoding unit, which parses an acquired transformation operation instruction, so as to obtain a transformation operation type indicated by an operation type field and obtain respective register serial numbers of the source address register, the destination address register, and the source tensor parameter register; and an instruction execution unit, which accesses the source address register, the destination address register, and the source tensor parameter register on the basis of their respective register serial numbers, reads a source memory address field, a destination memory address field, and a source tensor parameter, reads a source tensor on the basis of the source memory address field, performs, on the source tensor, a transformation operation indicated by the transformation operation type, and writes, on the basis of the source tensor parameter, a destination tensor obtained after the transformation operation into the destination memory address field.

Parallel processing computer systems and methods for real-time multimodal behavioral classification and dynamic content adaptation are provided. A parallel processing pipeline implements concurrent execution of sensor data ingestion, neural network inference, content adaptation, and rendering stages across specialized processor resources including graphics processing units and tensor processing units. The parallel processing pipeline achieves end-to-end latency of less than 200 milliseconds from sensor data capture to rendered content output, representing a reduction of at least 60% compared to conventional sequential architectures exhibiting latencies exceeding 500 milliseconds. A trained neural network model comprising feature extraction modules with parallel convolutional branches, a bidirectional Long Short-Term Memory temporal processing module, and a classification module processes multimodal sensor data including video frame data, audio waveform data, motion tracking data, and physiological sensor data to classify behavioral states and calculate engagement levels. A dynamic adjustment algorithm modifies content parameters including difficulty level, environmental complexity, and reinforcement schedule based on real-time performance metrics to maintain user performance within target ranges.

The invention belongs to the field of molecular dynamics calculation, and discloses a high-speed molecular dynamics calculation method based on CPU-TPU (central processing unit-thermoplastic polyurethane). According to the method, firstly, a computer system of a central processing unit (CPU) with a storage and calculation separation framework and a tensor unit (TPU) with storage and calculation integration and a deep learning special framework is constructed, and the CPU and the TPU communicate with each other through a high-speed interface. The CPU is responsible for processing complex logic operation, initializing molecular system information and simulation parameters set by a user, constructing an adjacent matrix, quickly transmitting data to the TPU through a high-speed interface and updating atomic speed and coordinates by utilizing the multi-core parallel computing capability. The TPU efficiently completes the step of calculating the atomic energy and the inter-atomic acting force by utilizing the advantages of storage and calculation integration and deep learning special architecture design, and transmits data to the CPU through a high-speed interface. According to the method, a high-speed transmission interface is used, the characteristics of high calculation frequency, multiple cores and suitability for complex logic calculation of the CPU are combined, and the characteristics of high calculation efficiency brought by storage and calculation integration and deep learning special architecture design of the TPU are combined, so that the molecular dynamics calculation process under the same precision is greatly accelerated.

A tensor calculation device, a data processor, a tensor calculation method and a storage medium. The tensor calculation device comprises a receiving unit, a tensor processing unit and an arithmetic processing unit; the tensor processing unit is configured to perform a first tensor calculation on a first tensor to obtain a first intermediate tensor; the tensor processing unit is further configured to obtain a virtual tensor and perform a second tensor calculation on a second tensor according to the virtual tensor to obtain a second intermediate tensor, wherein the second intermediate tensor and the second tensor have the same shape, and the numerical values of the elements at all corresponding positions of the second intermediate tensor and the second tensor have the same preset proportional relationship; and the arithmetic processing unit is configured to perform arithmetic operation processing on the second intermediate tensor and the first intermediate tensor to obtain a result tensor. The tensor calculation device does not need to load data for performing the arithmetic operation, and there is no bandwidth competition phenomenon, thereby greatly improving the overall efficiency of the operator and effectively utilizing the powerful computing power of the tensor calculation device itself.

Systems and methods for high-bandwidth, minimally invasive brain-computer interfaces (BCIs) are disclosed. The BCIs are configured for deployment and operation in conjunction with a comprehensive interventional electrophysiology procedural suite. Three primary methods of minimally invasive electrode array delivery are disclosed: (1) cortical surface delivery, (2) ventricular delivery, and (3) endovascular delivery. Additionally, systems and methods for interacting with such high-bandwidth electrode arrays are discussed, including real-time imaging, signal processing, and neural decoding. Systems and methods for architectures for accelerating the underlying computational processes (such as graphics processing units or tensor processing units) are also discussed. Multiple applications of BCIs are discussed, with emphasis on restoration, rehabilitation, and augmentation of neurologic function.

Systems and methods for high-bandwidth, minimally invasive brain-computer interfaces (BCIs) are disclosed. The BCIs are configured for deployment and operation in conjunction with a comprehensive interventional electrophysiology procedural suite. Three primary methods of minimally invasive electrode array delivery are disclosed: (1) cortical surface delivery, (2) ventricular delivery, and (3) endovascular delivery. Additionally, systems and methods for interacting with such high-bandwidth electrode arrays are discussed, including real-time imaging, signal processing, and neural decoding. Systems and methods for architectures for accelerating the underlying computational processes (such as graphics processing units or tensor processing units) are also discussed. Multiple applications of BCIs are discussed, with emphasis on restoration, rehabilitation, and augmentation of neurologic function.

Implementations described herein are directed to techniques for eliminating and / or mitigating memorization by machine learning (ML) model(s). Processor(s) can obtain a plurality of training instances to be utilized in training a ML model, identify a plurality of compute cores (e.g., TPUs, GPUs, CPUs, FPGAs, ASICs, etc.), and generate a corresponding per-core gradient at each of the plurality of compute cores. Further, the processor(s) can update the ML model based on the corresponding per-core gradients. In generating the corresponding per-core gradient at a given compute core, the processor(s) can generate corresponding gradients based on a subset of the training instances, determine, based on the corresponding gradients, a corresponding mean gradient, and clip, based on a clipping bound, the corresponding mean gradient for the given compute core to generate the corresponding per-core gradient.

The invention discloses a reconfigurable operator combination determination method and device for aided driving, and belongs to the technical field of electric digital data processing. The method comprises the following steps: acquiring key feature information of preset road condition data of a vehicle and hardware performance information of a tensor processing unit of the vehicle; selecting a candidate operator based on the key feature information and the hardware performance information, and determining a disturbance index of the candidate operator; pairing the candidate operators in pairs to obtain basic operator pairs, and determining matching scores of the basic operator pairs according to disturbance indexes of the candidate operators in the basic operator pairs; and selecting a preset number of basic operator pairs as candidate operator pairs according to the sequence of the matching scores from high to low, and determining a to-be-applied reconfigurable operator combination of the vehicle according to the candidate operator pairs. According to the technical scheme, reasonable screening of reconfigurable operator combinations is achieved by accurately matching road condition data features with TPU hardware features and quantizing operator cooperative disturbance influences, and therefore the real-time performance of auxiliary driving control is improved.

The embodiment of the invention provides a tensor data transformation method, a tensor processing unit, a processor, a system on chip and computing equipment. The tensor processing unit comprises a register array unit which at least comprises a source address register, a destination address register and a source tensor parameter register; the instruction decoding unit is used for analyzing the obtained transformation operation instruction, obtaining a transformation operation type indicated by an operation type field, and obtaining respective register numbers of a source address register, a destination address register and a source tensor parameter register; the instruction execution unit is used for respectively accessing a source address register, a destination address register and a source tensor parameter register according to the serial numbers of the registers, reading a source memory address field, a destination memory address field and a source tensor parameter, reading a source tensor according to the source memory address field, executing a transformation operation indicated by a transformation operation type on the source tensor, and sending the source tensor to the destination address register; and according to the source tensor parameter, writing the transformed target tensor into a target memory address field.

Various embodiments described herein dynamically control circuitry in a tensor processing unit (TPU) to efficiently cause arithmetic logic units (ALUs) to perform artificial intelligence (AI)-based operations, such as those involving matrix-matrix operations. Circuitry in the TPU is controlled based on a determination that ALUs are arranged to perform certain dot product operations over a plurality of clock cycles and that a subset of ALUs do not perform a dot product operation during a first clock cycle of the plurality of clock cycles. Controlling the circuitry in the TPU causes the TPU to repurpose the ALUs to cause at least a portion of the subset of ALUs to perform, during the first clock cycle, at least one dot product operation of the plurality of dot product operations. In this manner, more neural network operations can be performed per clock cycle, thereby improving computational efficiency, speed, and throughput using TPUs.

The invention discloses a server, and relates to the technical field of servers, the server comprises a case, an installation space is formed in the case, and a first installation port and a second installation port are formed in the two ends of the case respectively; the accelerator module is inserted into the installation space from the first installation port, and the accelerator module comprises any one of a graphics processor module, a tensor processor module and a neural network processor module; the central processing unit module and the accelerator module are arranged in a stacked mode. The plug-in box module is inserted into the installation space from the second installation opening, a first heat dissipation cavity and a second heat dissipation cavity which are independent of each other are formed in the plug-in box module, a first fan assembly is arranged in the first heat dissipation cavity, a second fan assembly is arranged in the second heat dissipation cavity, and the first heat dissipation cavity communicates with the accelerator module through a first heat dissipation channel; and the second heat dissipation cavity is communicated with the central processing unit module through a second heat dissipation channel. And each module in the case can perform independent heat dissipation, so that the problem of unreasonable air distribution is solved, and the technical effect of efficient heat dissipation is achieved.