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7results about "Discontinuous tuning with variable tuning element" patented technology

Tuning positioning control method and apparatus

ActiveCN116094493BDiscontinuous tuning with variable tuning elementSoftware engineeringEncoder
The application relates to a tuning positioning control method and device. A multi-turn absolute value encoder is used to collect the tuning position of a tuning device, the interval of the collected digital position value is far smaller than the precision range of analog-digital conversion, and the hardware or software can be set according to the actual required precision. The tuning precision is high, the error is small, and the tuning matching effect is optimal.
Owner:BEIJING BBEF SCI & TECH

Compact frequency adjustable portable antenna

PendingUS20250316905A1Simultaneous aerial operationsDiscontinuous tuning with variable tuning elementCapacitanceNoise
A compact mobile high-frequency Antenna that quickly and quietly self-adjusts to minimize Voltage Standing Wave Ratio (VSWR). Includes a compact tuning coil and a rolling contact. A Reentrant cap serves as a capacitive top hat. A spiral cut enhances the efficiency is this very short antenna. A tough insulating tube covers the antenna to serve as a radome protect the user from RF burns. The use of rolling contacts on a smooth inside diameter of the tuning coil greatly reduces the force to move the contactor as well as the acoustical noise generated when tuning. A controller drives a servo motor to position the contactor to the optimal position within the tuning coil and selects the impedance to connect between the unused end of the tuning coil and the feed point of the antenna to optimize VSWR.
Owner:COMPACT ANTENNAS LLC

Capacitive element and circuit structure including capacitive element(s)

Disclosed are a capacitive element (CE) and a circuit structure including CE(s). The CE includes series-connected first, second, and third transistors (dual-gate n-type field effect transistors). Shared source / drain regions between the second and first transistors and between the first and third transistors are connected to capacitors, respectively. The first transistor is larger than the second and third transistors. The front gate of the first transistor and back gates of all three transistors receive a first control voltage (VC1). The front gates of the second and third transistors receive a second control voltage (VC2). VC1 and VC2 are concurrently switchable to concurrently switch the three transistors between on and off states. High and low voltage levels of VC1 are at a first positive voltage level and at ground. High and low voltage levels of VC2 are at the first positive voltage level and at a second positive voltage level.
Owner:GLOBALFOUNDRIES US INC

Capacitive element and circuit structure including capacitive element

The invention relates to a capacitive element (CE) and a circuit structure comprising the CE. The CE includes first, second, and third transistors (dual gate n-type field effect transistors) connected in series. Shared source / drain regions between the second and first transistors and between the first and third transistors are respectively connected to a capacitor. The first transistor is larger than the second and third transistors. The front gate of the first transistor and the back gates of all three transistors receive a first control voltage (VC1). Front gates of the second and third transistors receive a second control voltage (VC2). The VC1 and the VC2 can be switched at the same time so as to switch the three transistors between an on state and an off state at the same time. A high voltage level and a low voltage level of VC1 are at a first positive voltage level and ground. The high voltage level and the low voltage level of the VC2 are at a first positive voltage level and a second positive voltage level.
Owner:GLOBALFOUNDRIES US INC

Capacitive element and circuit structure including capacitive element(s)

Disclosed are a capacitive element (CE) and a circuit structure including CE(s). The CE includes series-connected first, second, and third transistors (dual-gate n-type field effect transistors). Shared source / drain regions between the second and first transistors and between the first and third transistors are connected to capacitors, respectively. The first transistor is larger than the second and third transistors. The front gate of the first transistor and back gates of all three transistors receive a first control voltage (VC1). The front gates of the second and third transistors receive a second control voltage (VC2). VC1 and VC2 are concurrently switchable to concurrently switch the three transistors between on and off states. High and low voltage levels of VC1 are at a first positive voltage level and at ground. High and low voltage levels of VC2 are at the first positive voltage level and at a second positive voltage level.
Owner:GLOBALFOUNDRIES US INC