46results about How to "Few switch" patented technology

The present invention describes an electrical converter system for power supply systems, comprising at least two identical individual modules connected consecutively, characterised in that each individual module have at least four internal switching elements, at least one energy storage element and at least four connectors, wherein the connectors are paired and serve as a first and a second terminal pair; the internal switching elements of each individual module are designed in such manner that they are able to selectively connect one or both connectors of each terminal pair to the energy storage element; the cascaded connection of at least two individual modules is made in such manner that the connectors in the second terminal pair of a preceding individual module are each connected to the connectors of the first terminal pair in the respective following individual module, and at least one terminal of the first terminal pair of the first individual module of the cascaded connection and at least one terminal of the second terminal pair of the last individual module of the cascaded connection serve as terminals for the cascaded connection; and wherein the switching elements of the respective individual modules in the cascaded connection of at least two individual modules connect their respective energy storage element to the terminals of the cascaded connection in such manner that a selective serial or parallel connection of the energy storage elements is made.

A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input to receive at least one input signal and having an output at an internal enable node. A keeper circuit includes at least one switching element that is responsive to a gated clock signal and is coupled to the internal enable node to selectively hold a logical voltage level at the internal enable node. The system further includes a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.

Disclosed is an energy recovery device for recovering energy in a display panel, in particular a plasma display panel, wherein an energy recovery storing unit (L_recover) is coupled with the display panel during an energy recovery period following a sustain period. The particularity of the invention is that the energy recovery recover storing unit (L_recover) is charged in said sustain step.

An arcade game is disclosed having a modified three dimensional control of an acquisition device using three motors, pulleys, and belts that maneuver the acquisition device in three directions. Each belt is located in a pair of pulley wheels that have a “grooved section that allows the belt to slip when the motor reaches an end of its cycle, eliminating the need for switches and clutches.

Apparatus for controlling the voltage supplied to a load, comprising:

a multi-phase transformer having a primary and a secondary winding for each phase, each secondary being connected in series between an input line and an output directed to the load; and

the primary is configurable by switches such that the phase of the voltage of the secondary is different from the line to which it is connected by a phase different from 0 and 180 degrees.

A same instruction different operation (SIDO) processor is disclosed in which the instruction control word is supplied using data bus as one operand and the data to be operated is supplied through another operand. Also disclosed is a method for the provision of operation-code along with data/operands using a short instruction word. With all the execution units working in parallel on multiple data operands, a variety of operations can be performed in parallel. This allows short instruction format and flexibility to dynamically program the processor on the fly by changing data/operand words, and supports basic integer operations using very simple and efficient hardware execution units.

A scheduling algorithm is provided that may be implemented in a multi-stage switch requiring less switching elements than known switching architectures in order to increase bandwidth and to retain the non-blocking properties of the constituent switching elements for incoming traffic, including multicast traffic. A scheduling algorithm is also provided for incremental scheduling of connections being added or removed from the switch.

A DAC has an N-bit R-string DAC section and an (M-N)-bit interpolation DAC section. The N-bit R-string DAC section has a plurality of resistors and a 2-of-N selector. The resistors are electrically connected in series to provide a plurality of voltage levels. The 2-of-N selector is coupled to the series-connected resistors, and is arranged to select two neighboring voltage levels according to an N-bit MSB subword. The (M-N)-bit interpolation DAC section is coupled to the N-bit R-string DAC section, and is arranged to interpolate an analog output signal from the two neighboring voltage levels according to an (M-N)-bit LSB subword.