46results about How to "Few switch" patented technology

A clock gating system and method is disclosed. In a particular embodiment, the system includes an input logic circuit having at least one input to receive at least one input signal and having an output at an internal enable node. A keeper circuit includes at least one switching element that is responsive to a gated clock signal and is coupled to the internal enable node to selectively hold a logical voltage level at the internal enable node. The system further includes a gating element responsive to an input clock signal and to the logical voltage level at the internal enable node to generate the gated clock signal.

Methods and computer-executable components for real-time scheduling of CPU resources are disclosed. A performance counter determines when to allocate CPU resources to a thread. When it is time to allocate the CPU resources, the performance counter issues a maskable or non-maskable interrupt to an advanced programmable interrupt controller (APIC). The APIC then issues a maskable non-maskable interrupt to the CPU. In response to receiving the non-maskable interrupt, the CPU allocates resources to the thread. In addition, the disclosed methods and computer-executable components also: (a) allow scheduling of CPU resources such that real-time threads are guaranteed respective portions of time slots, (b) enable real-time scheduling on a non-real-time operating system, and (c) provide scheduling of CPU resources on a uni-processor machine such that at least first and second real-time threads dependent on one another are synchronized.

A DAC has an N-bit R-string DAC section and an (M-N)-bit interpolation DAC section. The N-bit R-string DAC section has a plurality of resistors and a 2-of-N selector. The resistors are electrically connected in series to provide a plurality of voltage levels. The 2-of-N selector is coupled to the series-connected resistors, and is arranged to select two neighboring voltage levels according to an N-bit MSB subword. The (M-N)-bit interpolation DAC section is coupled to the N-bit R-string DAC section, and is arranged to interpolate an analog output signal from the two neighboring voltage levels according to an (M-N)-bit LSB subword.

The present invention comprises a combination of a new circuit topology utilizing microcontroller (202, 302) and a modified logic control circuit which enables the replacement of a Schottky diode, commonly used in series with AC adapter, by a MOS transistor switch (212, 312) to implement airline mode operation of a system, with the added benefits of more efficient power dissipation and minimization of sparking or arcing at the power input terminal.

A multiprocessing transaction recovery manager, operable with a transactional application manager and a resource manager, comprises a threadsafety indicator for receiving and storing positive and non-positive threadsafety data of at least one transactional component managed by one of the transactional application manager and the resource manager; a commit protocol component for performing commit processing for the at least one transactional component; and a thread selector responsive to positive threadsafety data for selecting a single thread for the commit processing to be performed by the commit protocol component. The thread selector is further operable to select plural threads for the commit processing to be performed by the commit protocol component responsive to non-positive threadsafety data.

A single-structure, two-bit phase shifter useful for steering the beam of an antenna such as an aeronautical antenna. The phase shifter includes an input line, an output line, a plurality of switched lines such as quarter-wavelength microstrip lines connected directly or indirectly between the input line and the output line, and a plurality of switches for selectively and controllably connecting one or more of the switched lines between the input line and the output line. The phase shifter controllably connects one or more of the switched lines in series between the input line and the output line, thus providing phase shifts of an input radio frequency (RF) signal between one of four discrete phase shift amounts. Using up to three quarter-wavelength switched lines, the phase shifter provides phase shifts in increments of ninety degrees, e.g., phase shifts of zero, ninety, one hundred eighty, and two hundred seventy degrees (0°, 90°, 180°, and 270°). The inventive phase shifter is formed as a single two-bit structure, rather than two one-bit structures; thus it has a relatively smaller size than conventional two-bit phase shifters. Also, the inventive two-bit phase shifter may be configured such that the input signal passes through only one closed switch in any phase shift configuration, which reduces the overall insertion loss by reducing the insertion loss caused by passing the input signal through multiple switches.

The present invention provides a monolithic gate driver that includes fewer elements than in conventional configurations. In one aspect, a plurality of stages included in a shift register are divided into a plurality of stage circuit groups, where each stage circuit group includes the stage circuits of P adjacent stages (two stages, for example). Each stage circuit group includes a stabilization node and a stabilization node controller that controls the voltage of the stabilization node. The stabilization node controller includes: thin-film transistors in which the gate terminals thereof are connected to output control nodes, the drain terminals thereof are connected to the stabilization node, and the source terminals thereof are connected to an input terminal for a DC supply voltage; and a thin-film transistor for changing the voltage of the stabilization node to a high level.

A control circuit and method for a buck-boost switching converter provides a mode determinative circuit to judge the timing of an operation under buck-boost mode based on the input voltage, the output voltage and the mode reference voltage; meanwhile, the control signal generating circuit is provided to turn off the second switch during the first switch being on, turn on the second switch during the first switch being off, turn off the fourth switch during the third switch being on, turn on the fourth switch during the third switch being off, wherein the duty cycles of the first and third switches are identical, and duty cycles of the second and fourth switches are identical.

A DAC includes a gamma voltage generator for generating a plurality of gamma voltages, and a decoder for receiving an M-bit digital value for selecting one of the gamma voltages, wherein the decoder comprises a first thermometer encoder, a first selector and a second selector. The first thermometer encoder is utilized to receive N bits of the digital value to generate a first thermometer code with 2N bits, wherein N is smaller than M, and M and N are positive integers. The first selector has a plurality of selecting groups, each selecting group having 2N switches controlled by the first thermometer code to output one gamma voltage, where the second selector receives the gamma voltages outputted by the selecting groups of the first selector and outputs one gamma voltage selected from the received gamma voltages based on the (M−N) bit of the digital value.