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Multiprocessor node controller circuit and method

Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input / output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input / output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip. Optionally, the memory is packaged on plugable memory / directory cards wherein each card includes a plurality of memory chips including a first subset dedicated to holding memory data and a second subset dedicated to holding directory data. Further, the memory port includes a memory data port including a memory data bus and a memory address bus coupled to the first subset of memory chips, and a directory data port including a directory data bus and a directory address bus coupled to the second subset of memory chips. In some such embodiments, the ratio of (memory data space) to (directory data space) on each card is set to a value that is based on a size of the multiprocessor computer system.
Owner:HEWLETT-PACKARD ENTERPRISE DEV LP +1

Subminiature bone vibrating speaker using the diaphragm and mobile phone thereby

The present invention relates to a subminiature bone conduction speaker by using a vibrating plate and a mobile phone having the subminiature bone conduction speaker. A subminiature bone conduction speaker using a vibrating plate according to the present invention comprises a body having a shape of a cylinder of which upper portion is opened; yoke which is disposed in a lower portion of the body and of which center has a protrusion; a ring type magnet which is formed on the edge of the yoke and apart from an end portion of the protrusion by a predetermined clearance; an upper plate which is formed on the magnet; a mastoid which is contacted to bone conduction of a user and by which vibration is transmitted to the user; an acoustic vibrating plate which is inserted at a lower side of the mastoid to cover the opening portion of the body and which is made of an elastic material; an auxiliary vibrating plate which is inserted under the acoustic vibrating plate which is inserted to the mastoid; a voice coil which is attached to the auxiliary vibrating plate and which is inserted between the end portion of the protrusion of the yoke and the ring type magnet; a front cap for fixing the acoustic vibrating plate on the body; and a electrical signal input unit for inputting an electric signal to the voice coil.
Owner:LEE OUG KI +2

Multiprocessor node controller circuit and method

Improved method and apparatus for parallel processing. One embodiment provides a multiprocessor computer system that includes a first and second node controller, a number of processors being connected to each node controller, a memory connected to each controller, a first input / output system connected to the first node controller, and a communications network connected between the node controllers. The first node controller includes: a crossbar unit to which are connected a memory port, an input / output port, a network port, and a plurality of independent processor ports. A first and a second processor port connected between the crossbar unit and a first subset and a second subset, respectively, of the processors. In some embodiments of the system, the first node controller is fabricated onto a single integrated-circuit chip. Optionally, the memory is packaged on plugable memory / directory cards wherein each card includes a plurality of memory chips including a first subset dedicated to holding memory data and a second subset dedicated to holding directory data. Further, the memory port includes a memory data port including a memory data bus and a memory address bus coupled to the first subset of memory chips, and a directory data port including a directory data bus and a directory address bus coupled to the second subset of memory chips. In some such embodiments, the ratio of (memory data space) to (directory data space) on each card is set to a value that is based on a size of the multiprocessor computer system.
Owner:HEWLETT-PACKARD ENTERPRISE DEV LP +1
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