31results about How to "Output and" patented technology

A fault detection method for detects, within a semiconductor device, a fault in a delay chain that is provided within the semiconductor device and is made up of delay parts that are each formed by delay cells. The method judges if a fault exists in a first specific delay cell within a first delay part when testing the first specific delay cell, by detecting a first relative delay time between input and output signals of the first specific delay cell, and processing the first relative delay time at a timing based on an output of a delay cell within a second delay part that is provided at a stage preceding or subsequent to the first delay part. The method judges if a fault exists in a second specific delay cell within the second delay part exists when testing the second specific delay cell, by detecting a second relative delay time between input and output signals of the second specific delay cell, and processing the second relative delay time at a timing based on an output of a delay cell within the first delay part.

Methods and systems are provided for calibrating a compressor surge line. In one example, a method may include adjusting the compressor surge line based on a vehicle speed in addition to a compressor pressure ratio. For example, at higher vehicle speeds, above a threshold vehicle speed, a less aggressive surge line calibration may be utilized in order to improve drivability while at lower vehicle speeds, below the threshold vehicle speed, a more aggressive surge line calibration may be utilized for NVH mitigation.

A system for input and output of data with non-standard I / O devices for web and other applications. In one aspect, non-standard input data is received from the non-standard input device at a client, and the non-standard input data is provided as equivalent standard input data to the standard browser running on the client, so that the standard browser can submit the input data to an application running on a server in communication with the client over a network. In another aspect, a server receives a request from a user, and requested data and instructions are sent to the client, where a standard browser running on the client receives the data and instructions and the data can be sent to be output by a non-standard output device in communication with the client.

In a two-port non-reciprocal circuit device, connecting portions of a first central electrode are electrically connected to first and second balanced input terminals, respectively. Likewise, connecting portions of a second central electrode are electrically connected to first and second balanced output terminals, respectively. First and second resistors are electrically connected between the first balanced input terminal and the first balanced output terminal and between the second balanced input terminal and the second balanced output terminal, respectively. First to fourth matching capacitors are electrically connected between the connecting portions of the first and second central electrodes and ground, respectively.

Methods and systems are provided for calibrating a compressor surge line. In one example, a method may include adjusting the compressor surge line based on a vehicle speed in addition to a compressor pressure ratio. For example, at higher vehicle speeds, above a threshold vehicle speed, a less aggressive surge line calibration may be utilized in order to improve drivability while at lower vehicle speeds, below the threshold vehicle speed, a more aggressive surge line calibration may be utilized for NVH mitigation.

Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.

Provided are a non-aqueous electrolyte solution, which includes (i) a first lithium salt, (ii) lithium bis(fluorosulfonyl)imide as a second lithium salt, (iii) a phosphazene-based compound as a first additive, and (iv) a non-aqueous organic solvent, and a lithium secondary battery including the non-aqueous electrolyte solution.With respect to a lithium secondary battery including the non-aqueous electrolyte solution of the present invention, since a robust solid electrolyte interface (SEI) may be formed on the surface of a negative electrode during initial charge and flame retardancy in a high-temperature environment may be provided to prevent the decomposition of the surface of a positive electrode and an oxidation reaction of the electrolyte solution, output characteristics and capacity characteristics after high-temperature storage as well as output characteristics may be improved.

Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and outgoing pixel rate is maintained without additional clock cycles or memory bandwidth as an improved timing control according to the present invention takes advantage of idle memory bandwidth by pre-fetching a new column of pixel data in a first pixel block of a next line or frame while a new column of an edge pixel block on a current line is duplicated or zeroed out. As the edge pixel block(s) on the current line are processed, the data in the first pixel block of the next line or frame become ready for computation without extra clock cycles or extra memory bandwidth.