31results about How to "Reduced circuit layout area" patented technology

An active device and an active device array substrate are provided, wherein the active device array substrate includes a substrate and a plurality of active devices being located on the substrate, and at least one of the active devices includes a first thin film transistor and a second thin film transistor. The first thin film transistor is located on the substrate and has a first channel layer. The second thin film transistor stacks on the first thin film transistor, wherein the second thin film transistor has a second channel layer. The first thin film transistor and the second thin film transistor share a common gate electrode and the common gate electrode is located between the first channel layer and the second channel layer.

An electrostatic discharge (ESD) clamp circuit is provided. The ESD clamp circuit includes a first resistor, a second resistor, a first transistor, a second transistor, and a third transistor. A clamp device of the ESD clamp circuit is implemented by the third transistor. A parasitic capacitor of the third transistor forms a detection scheme along with the second resistor to detect the ESD. The first resistor, the second resistor, the first transistor, and the second transistor form a feedback scheme to control the third transistor for discharging the ESD current.

A digital pulse-width control apparatus including an input module, a digital delay locked loop, a plurality of programmable delay circuits connected in series, and a pulse-width modulation module is provided. The present invention uses the input module to vary a clock signal to reduce the limitation of a duty cycle of the clock signal to the digital pulse-width control apparatus.

A shift register without a feedback signal of a post-stage shift register utilizing a latch mechanism and a clock signal to control the voltage of an output of the shift register is provided. The shift register reduces the transistor size and the circuit layout area. The shift register also improves the issue the overlapping between two adjacent shift registers to reduce the after-image of a liquid crystal display.

A digital pulse-width control apparatus including an input module, a digital delay locked loop, a plurality of programmable delay circuits connected in series, and a pulse-width modulation module is provided. The present invention uses the input module to vary a clock signal to reduce the limitation of a duty cycle of the clock signal to the digital pulse-width control apparatus.

A touch sensing device includes a touch sensing trace layout, a comparator and a variable capacitor unit. The touch sensing trace layout performs a sensing operation according to at least one first driving signal in a sensing state. An input of the comparator is electrically coupled to the touch sensing trace layout for receiving a sensing signal outputted by the touch sensing trace layout. The variable capacitor unit is selectively coupled to one of the inputs of the comparator, for correspondingly performing potential compensation to the sensing signal received by the input of the comparator according to at least one second driving signal.

A source driver and a Gamma correction method thereof with lower layout area and preferred Gamma correction performance are provided. The source driver includes a Gamma correction unit, a latch unit, and a digital-to-analog converter (DAC). The Gamma correction unit receives an original image data, and converts the original image data to a corresponding corrected image data. The latch unit is coupled to the Gamma correction unit. The DAC is coupled to the latch unit, so as to convert the corrected image data to a corresponding analog drive signal. In the Gamma correction method, first, a correction unit to correct an original image data to a corresponding corrected image data is provided, and the corrected image data is converted into a corresponding analog drive signal.

A bit line potential monitor circuit is provided in a bit line, and a step-down circuit of the bit line is controlled base on information from the monitor circuit. As a result, the bit line is easily stepped down to an optimal potential level in accordance with a potential and a load capacity thereof without being affected by variability in devices or operation conditions.

A display control device has: a shift register generating n shift pulses in series; a data hold block configured to hold n gradation data; and a DA converter for converting the n gradation data into corresponding gradation voltages. The data hold block includes: n first latch circuits configured to respectively latch the n gradation data in series in synchronization with the n shift pulses; and n second latch circuits provided between the DA converter and the n first latch circuits. An electrical connection between the first latch circuits and the second latch circuits is cut off while the first latch circuits receive the n gradation data. After the first latch circuits finish latching all the gradation data, the n gradation data are simultaneously supplied to the DA converter from the first latch circuits through the second latch circuits.

A shift register without a feedback signal of a post-stage shift register utilizing a latch mechanism and a clock signal to control the voltage of an output of the shift register is provided. The shift register reduces the transistor size and the circuit layout area. The shift register also improves the issue the overlapping between two adjacent shift registers to reduce the after-image of a liquid crystal display.

A method pixel driving method of an organic light emitting diode (OLED) display and an apparatus thereof are provided. The method comprises the following steps. First, a pixel unit is reset to a predetermined voltage in a reset time period. After that, a frame period is divided into two driving time periods so that the pixel unit is finally charged to a pixel voltage. The charging process of the pixel unit is that the pixel unit is charged to a ground level in a first driving time period, and then the pixel unit is charged to the pixel voltage in a second driving time period.

An electrostatic discharge (ESD) clamp circuit is provided. The ESD clamp circuit includes a first resistor, a second resistor, a first transistor, a second transistor, and a third transistor. A clamp device of the ESD clamp circuit is implemented by the third transistor. A parasitic capacitor of the third transistor forms a detection scheme along with the second resistor to detect the ESD. The first resistor, the second resistor, the first transistor, and the second transistor form a feedback scheme to control the third transistor for discharging the ESD current.

A display control device has: a shift register generating n shift pulses in series; a data hold block configured to hold n gradation data; and a DA converter for converting the n gradation data into corresponding gradation voltages. The data hold block includes: n first latch circuits configured to respectively latch the n gradation data in series in synchronization with the n shift pulses; and n second latch circuits provided between the DA converter and the n first latch circuits. An electrical connection between the first latch circuits and the second latch circuits is cut off while the first latch circuits receive the n gradation data. After the first latch circuits finish latching all the gradation data, the n gradation data are simultaneously supplied to the DA converter from the first latch circuits through the second latch circuits.

A level-shifting apparatus and a panel display apparatus using the same are disclosed. The level-shifting apparatus is used for receiving and changing the level of an input signal to generate an output signal. The level-shifting apparatus includes a first unit and a second unit. The first unit is for deciding whether a first switching signal and a second switching signal are to be output according to the input signal and the output signal. The second unit generates the output signal according to the first switching signal and the second switching signal. Wherein, the input signal is operated between a first level and a second level, while the output signal is operated between a third level and a fourth level.

A bit line potential monitor circuit is provided in a bit line, and a step-down circuit of the bit line is controlled base on information from the monitor circuit. As a result, the bit line is easily stepped down to an optimal potential level in accordance with a potential and a load capacity thereof without being affected by variability in devices or operation conditions.

Both a video integrated circuit that is connected to a video display apparatus for processing and displaying a plurality of video signals, and the video display apparatus thereof, are provided. The video integrated circuit and the video processing apparatus comprise a processor, a video capture unit, a watermark generating unit, a codec, and a video output unit. The video capture unit receives a digital video signal in response to a first signal from the processor to generate a processing signal. The watermark generating unit receives the processing signal in response to a second signal from the processor, and then embeds a watermark into a video corresponding to the processing signal to generate an integrated signal. The codec receives and compresses the integrated signal in response to a third signal from the processor, and then generates a compressed signal. The video output unit outputs the compressed signal to the video display apparatus in response to a fourth signal from the processor.

An active device and an active device array substrate are provided, wherein the active device array substrate includes a substrate and a plurality of active devices being located on the substrate, and at least one of the active devices includes a first thin film transistor and a second thin film transistor. The first thin film transistor is located on the substrate and has a first channel layer. The second thin film transistor stacks on the first thin film transistor, wherein the second thin film transistor has a second channel layer. The first thin film transistor and the second thin film transistor share a common gate electrode and the common gate electrode is located between the first channel layer and the second channel layer.

The present invention relates to an output stage circuit and an operational amplifier thereof. In the output stage circuit, one of a gate of a transistor is coupled to a gate of a bias transistor and a level shifter in response to a small signal outputted from an amplifying circuit in the operational amplifier. In addition, a gate voltage of the bias transistor is controlled by a voltage generating circuit to control a DC bias of the transistor of the output stage circuit. Therefore, there is no need extra frequency compensating component for compensating the transistor of the output stage circuit, and to save circuit layout area and cost can be achieved by the present invention.

A voltage switching device is used to receive several input voltage and output switch voltage; it includes the first switching unit, the second switching unit and the self bias voltage unit. The voltage switching device generates the switching voltage according to the output of the first switch unit and the second switching unit. The reference voltage output by the self bias voltage unit is sent to the second switch unit. The first switching unit outputs the first input voltage as the switching voltage according to the first energy signal. The second switch unit outputs the second input voltage as the switching voltage according to the second energy signal.

The invention relates to the technical field of trickle charging, in particular to a trickle charging circuit, a charger and an electronic device. The circuit comprises a trickle current control circuit, a path management circuit, a voltage detection circuit and a charging management chip. The voltage detection circuit is used for detecting an input power supply voltage and sending a power supplyvoltage value to the path management circuit. The path management circuit is used for receiving the power supply voltage value, comparing the power supply voltage value with the battery voltage valueof the to-be-charged battery, and closing an access between the charging management chip and the power supply end when the battery voltage value is smaller than the power supply voltage value. The trickle current control circuit is used for carrying out trickle charging on the battery to be charged when an access between the charging management chip and the power supply end is closed. When the voltage of the battery is too low, the current charging mode can be converted into a trickle charging mode so as to prevent the battery from being damaged due to the fact that large current is poured into a low-voltage battery, the charging efficiency is improved, and the to-be-charged battery is protected.

An electrostatic discharge (ESD) protection circuit includes a first transistor, a second transistor, a capacitor, a voltage dividing circuit, and a first diode. The first transistor is coupled between a first power rail and a second power rail. The second transistor is coupled between the first power rail and the second power rail. A bulk of the second transistor is coupled to a control terminal of the first transistor. The capacitor is coupled between the first power rail and a control terminal of the second transistor. The voltage dividing circuit is coupled between the control terminal of the second transistor and the second power rail, and has a divided voltage output terminal coupled to the bulk of the second transistor. The first diode is coupled between the divided voltage output terminal and the second power rail.

A magnetic field sensing apparatus and a detection method thereof are provided. The magnetic field sensing apparatus includes first and second AMR resistors, a current generator, and an arithmetic device. A magnetized direction of the first AMR resistor is set as a first direction. A magnetized direction of the second AMR resistor is set as a second direction opposite to or the same as the first direction. The current generator provides a current in a direction parallel to the first direction to flow through the first and second AMR resistors. The arithmetic device obtains a first detection voltage according to a voltage difference between two terminals of the first AMR resistor, obtains a second detection voltage according to a voltage difference between two terminals of the second AMR resistor, and performs his an arithmetic operation on the first and second detection voltages to obtain a first magnetic field detection result.

A magnetic field sensing apparatus and a detection method thereof are provided. The magnetic field sensing apparatus includes first and second AMR resistors, a current generator, and an arithmetic device. A magnetized direction of the first AMR resistor is set as a first direction. A magnetized direction of the second AMR resistor is set as a second direction opposite to or the same as the first direction. The current generator provides a current in a direction parallel to the first direction to flow through the first and second AMR resistors. The arithmetic device obtains a first detection voltage according to a voltage difference between two terminals of the first AMR resistor, obtains a second detection voltage according to a voltage difference between two terminals of the second AMR resistor, and performs his an arithmetic operation on the first and second detection voltages to obtain a first magnetic field detection result.

A high-voltage metal-oxide-semiconductor (HV MOS) transistor is provided to form the decoder in a source driver of a display apparatus for substantially saving the layout area. The HV MOS transistor includes two doped regions with a first conductivity type disposed in a semiconductor substrate, and a gate region having a second conductivity type opposite to the first conductivity type on the semiconductor substrate and between the doped regions. Accordingly, the layout area could be substantially reduced.

A touch sensing device includes a touch sensing trace layout, a comparator and a variable capacitor unit. The touch sensing trace layout performs a sensing operation according to at least one first driving signal in a sensing state. An input of the comparator is electrically coupled to the touch sensing trace layout for receiving a sensing signal outputted by the touch sensing trace layout. The variable capacitor unit is selectively coupled to one of the inputs of the comparator, for correspondingly performing potential compensation to the sensing signal received by the input of the comparator according to at least one second driving signal.