The invention relates to a novel laminated
diode manufacturing process and a
chip sieve tray thereof. The novel laminated
diode manufacturing process is characterized by comprising the following steps of forming a wide groove in the P surface or the N surface of a
silicon wafer, wherein the groove is 70 to 250 mum in width and 60 to 100 mum in depth; scribing in the way that the center of the bottom of the wide groove serves as a boundary; after filling a lead and sieving a
chip,
welding and fixing the
chip and the lead by using a
welding material, and when the chip is sieved, matching a small surface formed by forming the wide groove with a profile hole of the chip
sieve tray to identify the polarity of the P surface or the N surface; and sequentially performing
acid washing, strip
combing,
sizing, glue curing, mould pressing,
post curing,
electroplating, testing, character printing, packaging and goods delivery. Due to the steps of forming the wide groove in the P surface or the N surface of the
silicon wafer, scribing in the way that the center of the bottom of the wide groove serves as the boundary, matching the small surface formed by forming the wide groove with the profile hole of the chip
sieve tray to automatically identify and adjust the polarity of the P surface or the N surface, manual identification is not required, the efficiency and the accuracy are effectively improved, and the damage to the chip caused by manual adjustment with a nipper is avoided.