An integrated gate driver circuit receives a plurality of clocks and includes a plurality of driving units cascaded in series. Each driving unit is for driving a load and includes an input terminal, an output terminal, a first switch and a second switch. The first switch has a first terminal coupled to the input terminal, a second terminal coupled to a first node, and a control terminal receiving a first clock, and the first switch is turned on when the first clock is at high level. The second switch has a first terminal receiving a second clock, a second terminal coupled to the output terminal, and a control terminal coupled to the first node, wherein the second clock charges and discharges the load through the second switch when the first node is at high level; wherein the output terminal of each driving unit is coupled to the input terminal of the immediately succeeding driving unit.