35results about How to "Suppression of avalanche effects" patented technology

A structure is for increasing performance of transistors of GaN base high electronic movability includes: a sapphire substrate, a SiC2 substrate or a silicon substrate, a high resistance semi-insulation GaN buffer layer processed on the substrate, a high movability GaN channel layer processed on the buffer layer, a thin ALN plug-in layer processed on the channel layer to increase the integrated performance of the transistor materials of GaN base high electronic movability, a n-type doped or un-purpose doped ALGaN barrier layer processed on the thin ALN plug-in layer.

The invention discloses an III nitride MISHEMT device, which comprises source and drain electrodes, main and secondary grids, first and second medium layers and a heterostructure; the source and drain electrodes are electrically connected through two-dimensional electron gas formed in the heterostructure; the heterostructure comprises first and second semiconductors; the first semiconductor is arranged between the source and drain electrodes; the second semiconductor is formed on the surface of the first semiconductor and is provided with a band gap wider than the first semiconductor; the first medium layer is arranged on the surface of the second semiconductor and forms a metal insulation layer semiconductor contact (MIS) along with the second semiconductor and the main grid; the second medium layer is arranged on the surfaces of the first medium layer and the main grid and forms electric isolation for the main grid and the secondary grid; the main grid is arranged at one side of thesurface of the first medium layer close to the source electrode; and the secondary grid is formed on the surface of the second medium layer, and at least one side edge of the secondary grid is extended to the direction of the source electrode or the drain electrode, and meanwhile orthographic projection of the secondary grid is overlapped with the two side edges of the main grid. The ''current collapse effect'' can be substantially and effectively inhibited by the III nitride MISHEMT device.

The invention relates to a high-breakdown-voltage GaN-based high-electron-mobility transistor, which mainly comprises a substrate, an AlN nucleation layer, a GaN buffer layer, a GaN channel layer, a AlGaN barrier layer, a source electrode, a drain electrode and a grid electrode, wherein the above layers are successively arranged from bottom to top and the source electrode, the drain electrode and the grid electrode are formed on the AlGaN barrier layer. The high-breakdown-voltage GaN-based high-electron-mobility transistor is characterized by further comprising an AlxGa1-xN polarization doped layer positioned on the AlGaN barrier layer and between the grid electrode and the drain electrode, with the content of Al component to be gradually changed. The content of Al component in the AlxGa1-xN polarization doped layer is linearly increased from top to bottom. The three-dimensional hole gas generated caused by he gradually changing content of Al component and the two-dimensional electron gas of the channel layer compensate each other to form a charge self-balancing type super-junction structure. In this way, the charge imbalance problem is solved. Meanwhile, the breakdown voltage and the stability of equipment are improved.

The invention discloses a Group-III nitride HEM (High Electron Mobility Transistor) device which comprises a source electrode, a drain electrode, a main grid, an auxiliary grid, an insulating dielectric layer and a heterojunction structure; the source electrode and the drain electrode are electrically connected through two-dimension electron gas formed in the heterojunction structure; the heterojunction structure comprises a first semiconductor and a second semiconductor; the second semiconductor is formed on the surface of the first semiconductor and is provided with a band gap wider than the first semiconductor; the first semiconductor is arranged between the source electrode and the drain electrode; the main grate is arranged on the surface of the second semiconductor near one side of source electrode and is in schottky contact with the second semiconductor; the dielectric layer is formed on the second semiconductor and the surface of the main grid and is arranged between the source electrode and the drain electrode; the auxiliary grid is formed on the surface of the dielectric layer; at least one side edge of the auxiliary grid is extended toward the direction of the source electrode or the drain electrode; meanwhile, an orthographic projection of the auxiliary grid are overlapped with two side edges of the main grate. The Group-III nitride HEM device can fundamentally and effectively inhibit 'Current Collapse Effect'.

The invention discloses a group III nitride enhancement mode HEMT (High Electron Mobility Transistor) device which comprises source and drain electrodes, main and accessory grids, an insulating medium layer and a heterostructure, wherein the source and drain electrodes are electrically connected by two-dimensional electron formed in the heterostructure; the heterostructure comprises a first semiconductor and a second semiconductor; the first semiconductor is arranged between the source and drain electrodes; the second semiconductor is formed on the surface of the first semiconductor and is provided with a band gap which is wider than the first semiconductor; the main grid is arranged at one side of the surface of the second semiconductor near the source electrode and forms schottky contact with the second semiconductor, and a plasma processing area is also formed in the local area of the second semiconductor under the main grid; a medium layer is formed on the surfaces of the second semiconductor and the main grid and between the source and drain electrodes; and the accessory grid is formed on the surface of the medium layer, the edge of at least one side of the accessory grid extends to the direction of the source electrode or drain electrode, and the orthographic projection of the accessory grid is laminated with the edges of both sides of the main grid. The group III nitride enhancement mode HEMT device can effectively inhibit the current collapse effect fundamentally.

The invention discloses a manufacturing method of a T-shaped gate of a GaN-based FET (Field Effect Transistor). The manufacturing method comprises the steps of coating an electron beam photoresist on the surface of a substrate; carrying out exposure and development on the electron beam photoresist, and forming an etching window; etching the substrate from the formed etching window, and forming a fine gate graph of the T-shaped gate; evaporating a metal thin layer, and then secondly coating the electron beam photoresist; carrying out electron beam exposure and development on the electron beam photoresist which is secondly coated, removing the metal thin layer, and forming a T-shaped gate graph; evaporating deposited gate metal on the electron beam photoresist which is secondly coated and the T-shaped gate graph, stripping the electron beam photoresist which is secondly coated and the gate metal on the electron beam photoresist which is secondly coated, and forming the T-shaped gate. By utilizing the manufacturing method disclosed by the invention, the current collapse is effectively restrained, the stray capacitances of a gate source and a gate drain are reduced, the gate resistance of a device is reduced, the cut-off frequency (ft) and the maximum oscillation frequency (fmax) of the device are increased, and thus the device can work in an MMW (Millimeter Wave) frequency band.

The invention discloses a gallium nitride power device with a multi-field plate structure. The gallium nitride power device is sequentially provided with a substrate, a nucleating layer, a buffer layer, a first insertion layer, a first GaN layer, a second insertion layer, a second GaN layer, an AlGaN barrier layer, a passivation layer, a grid electrode field plate, a drain electrode field plate, aprotective layer, a grid electrode insertion layer, a p-type GaN grid electrode, a grid electrode metal, a source electrode metal and a drain electrode metal from bottom to top, wherein the passivation layer located on the surface of the AlGaN barrier layer is in a strip shape arranged at intervals, the grid electrode field plate and the drain electrode field plate respectively cover part of thepassivation layer, and the surfaces of the grid electrode field plate and the drain electrode field plate and the space between the grid electrode field plate and the drain electrode field plate are covered with the protective layer. According to the invention, the electric field distribution is uniform, the voltage endurance capability of the device is enhanced, the stability of grid electrode turn-on voltage and grid electrode voltage of the device is effectively improved, and the electric leakage of the device under the action of large current is effectively reduced. The preparation methodis completely compatible with a traditional process, and the preparation difficulty is low.

The invention provides a normally-closed gallium nitride HEMT device. The device comprises a heterostructure as well as a source electrode, a drain electrode and grid electrode which are connected with the heterostructure, wherein the heterostructure comprises a first semiconductor layer as a channel layer; a second semiconductor layer as a barrier layer is formed on the first semiconductor layer;a p-type semiconductor layer is formed between the second semiconductor layer and the grid electrode, two-dimensional electron gas is produced between the first semiconductor layer and the second semiconductor layer and disappears right below the p-type semiconductor layer; and a dielectric layer as a passivation layer is settled on the upper surface of the heterostructure, and pre-selected metalions are injected into the dielectric layer right above a region in which the two-dimensional electron gas usually exits. By virtue of each embodiment provided by the invention, the density of the two-dimensional electron of the normally-closed HEMT device can be effectively increased.

The invention discloses a gallium nitride transistor structure and a preparation method thereof. The gallium nitride transistor structure includes: a substrate 1; a GaN-based buffer layer 2 located onthe substrate 1; an InxAlyGa1-x-yN/GaN heterojunction epitaxial structure positioned on the GaN-based buffer layer 2; a source electrode 6 positioned at one end of the surface of the InxAlyGa1-x-yN/GaN heterojunction epitaxial structure; a drain electrode 5 positioned at the other end of the surface of the InxAlyGa1-x-yN/GaN heterojunction epitaxial structure; and a p-type oxide film and a gate 7which are located at the surface of the InxAlyGa1-x-yN/GaN heterojunction epitaxial structure. The p-type oxide film is arranged between the source electrode 6 and the drain electrode 5 at the surface of the InxAlyGa1-x-yN/GaN heterojunction epitaxial structure to obtain the GaN transistor structure of the p-type oxide intercalation to suppress the current collapse effect, and the virtual gate effect is relieved by neutralizing electrons in the hole in the p-type oxide and captured by surface traps.

An AlGaN-GaN high-electron mobility transistor with a P-type buried layer comprises a Si-based substrate, wherein an AlN nucleating layer is formed on the Si-based substrate, an intrinsic GaN layer is formed on the AlN nucleating layer, an AlGaN doping layer is formed on the intrinsic GaN layer, a gate oxide layer is formed on an upper surface of the AlGaN doping layer, a gate is formed on an upper surface of the gate oxide layer, a passivation layer covers the AlGaN doping layer and the gate, a source is formed at one side of the gate, a drain is formed at the other side of the gate, the source and the drain extend form an upper part of the intrinsic GaN layer, penetrate through the AlGaN doping layer and are stopped in the passivation layer, the AlGaN-GaN high-electron mobility transistor is characterized in that a P-type AlGaN doping region buried layer is formed in the AlN nucleating layer, an upper surface of the P-type AlGaN doping region buried layer is in contact with a lower surface of the intrinsic GaN layer, a boundary of the P-type AlGaN doping region buried layer is arranged below the gate, and the other boundary of the P-type AlGaN doping region buried layer is arranged below a region between the gate and the drain.