35results about How to "Suppression of avalanche effects" patented technology

The invention relates to the technical field of production of wide bandgap semiconductor materials and devices and discloses a method for improving the performance of a GaN-based field-effect transistor, the method comprises: mixed pre-treatment solution is adopted to carry out the surface pre-treatment of the surface of a device before the passivation of the GaN-based field-effect transistor during the production process of the GaN-based field-effect transistor, then a compound dielectric layer of silicon nitride and oxygen-rich silicon nitride is deposited on the surface of the device afterthe surface pre-treatment, and the GaN-based field-effect transistor is passivated. The use of the method can solve a surface original oxide layer which is existed on the surface of AlGaN for a long time, eliminate the AlGaN surface state which is induced by the surface oxide layer, solve the surface state existing in an AlGaN and silicon nitride interface, the current collapse effect which is induced by the surface original oxide layer and the significant increase of the reverse gate leakage current caused by the conventional passivation and improve the stability and the reliability of GaN-based HEMT.

The invention discloses an enhanced HEMT device with a back field plate structure and a preparation method thereof. The enhanced HEMT device with the back field plate structure can be manufactured through the commonly seen semiconductor device processing technology and comprises a source electrode, a drain electrode, a heterostructure and a back field plate electrode, wherein the source electrode and the drain electrode are electrically connected through two-dimensional electronic gas in the heterostructure, and the source electrode, the drain electrode and the heterostructure are of an ohmic contact mode; the heterostructure comprises a first semiconductor layer and a second semiconductor layer which are sequentially arranged in a set direction, the first semiconductor layer is arranged between the source electrode and the drain electrode, and the surface of the first semiconductor layer is provided with a grid electrode; a two-dimensional electron gas depletion area is arranged in the area inside the heterostructure, which corresponds to the grid electrode; the grid electrode is in Schottky contact with the first semiconductor layer; the back field plate electrode is arranged on the surface of the second semiconductor layer, which is away from the first semiconductor layer. The enhanced HEMT device with the back field plate can effectively increase the breakdown voltage of the device and restrain the current collapse effect to the largest extent.

The invention discloses a gallium nitride transistor structure and a preparation method thereof. The gallium nitride transistor structure includes a substrate 1; a GaN-based buffer layer 2 on the substrate 1; an In on the GaN-based buffer layer 2. x al y Ga 1‑x‑y N / GaN heterojunction epitaxial structure; on In x al y Ga 1‑x‑y The source 6 at one end of the surface of the N / GaN heterojunction epitaxial structure; x al y Ga 1‑x‑y The drain 5 at the other end of the surface of the N / GaN heterojunction epitaxial structure; x al y Ga 1‑x‑y The p-type oxide thin film and the gate 7 on the surface of the N / GaN heterojunction epitaxial structure. The present invention is passed in In x al y Ga 1‑x‑y A p-type oxide film is set between the source 6 and the drain 5 on the surface of the N / GaN heterojunction epitaxial structure, and the GaN transistor structure obtained by p-type oxide intercalation can suppress the current collapse effect, and utilize the p-type oxide The holes neutralize the electrons trapped by the surface traps, alleviating the dummy gate effect.

The invention discloses an III nitride MISHEMT device, which comprises source and drain electrodes, main and secondary grids, first and second medium layers and a heterostructure; the source and drain electrodes are electrically connected through two-dimensional electron gas formed in the heterostructure; the heterostructure comprises first and second semiconductors; the first semiconductor is arranged between the source and drain electrodes; the second semiconductor is formed on the surface of the first semiconductor and is provided with a band gap wider than the first semiconductor; the first medium layer is arranged on the surface of the second semiconductor and forms a metal insulation layer semiconductor contact (MIS) along with the second semiconductor and the main grid; the second medium layer is arranged on the surfaces of the first medium layer and the main grid and forms electric isolation for the main grid and the secondary grid; the main grid is arranged at one side of the surface of the first medium layer close to the source electrode; and the secondary grid is formed on the surface of the second medium layer, and at least one side edge of the secondary grid is extended to the direction of the source electrode or the drain electrode, and meanwhile orthographic projection of the secondary grid is overlapped with the two side edges of the main grid. The ''current collapse effect'' can be substantially and effectively inhibited by the III nitride MISHEMT device.

The invention designs power semiconductor technology, specifically a GaN heterojunction field effect transistor with low junction temperature and high withstand voltage. The GaN heterojunction field effect transistor of the present invention mainly lowers the peak electric field of the channel by inserting an AlN region in the barrier layer, thereby achieving the purpose of increasing withstand voltage and reducing heat dissipation. In addition, the present invention uses AlN with good thermal conductivity as the passivation layer of the device, which not only helps to suppress current collapse, but also accelerates heat dissipation. The excellent effect of the invention is that the reverse withstand voltage of the device is improved, the output characteristics of the device are improved, and the channel temperature of the device is reduced, thereby suppressing the harm caused by the current collapse and the self-heating effect. The invention is especially suitable for GaN heterojunction field effect transistors with high withstand voltage capability and low channel temperature.

A gallium nitride-based double heterojunction field effect transistor structure comprises a substrate, a low temperature gallium nitride layer or high temperature aluminum nitride layer formed on thesubstrate; a high insulation layer with unintentional-doped or doped gallium nitride; the high insulation layer with unintentional-doped or doped gallium nitride is formed on a low temperature galliumnucleation layer or a high temperature gallium nitride nucleation layer; a first aluminum nitride inserting layer, the first aluminum nitride inserting layer is formed on the high insulation layer with unintentional-doped or doped gallium nitride; a unintentional-doped gallium nitride channel layer, the unintentional-doped gallium nitride channel layer is formed on the first aluminum nitride inserting layer; a second aluminum nitride inserting layer, the second aluminum nitride inserting layer is formed on the unintentional-doped gallium nitride channel layer, an unintentional-doped or n-typedoped AlxInyGazN layer, the unintentional-doped or n-type doped AlxInyGazN layer is formed on the second aluminum nitride inserting layer.