A
solid state imager converts analog pixel values to digital form on an arrayed per-column basis. A counter is coupled to an N-bit DAC to produce an analog ramp that varies corresponding to the contents of the counter. A
ripple counter is associated with each respective column. A
clock or a source of counts at a predetermined sequence supplies
clock signals or counts to the counter elements. Column comparators gate the counter elements when the analog ramp equals the pixel value. The counter contents feed a
video output bus to produce the
digital video signal. Additional black-level readout counters elements can create and store a
black level digital value that is subtracted from the pixel value to reduce
fixed pattern noise. The counters may employ two's complement arithmetic. An additional array of buffer counter / latches can be employed.
Ripple counters can be configured as counters to capture the
digital video level, and then as shift registers to
clock out the video levels to an output
bus. The clock pulses or counts for the DAC counter and for the
ripple counters can be at the same or different rates.