115results about How to "Prevent capacitance" patented technology

In order to provide an active matrix display device in which parasitic capacitance or the like is suppressed by forming a thick insulating film around an organic semiconductor film and disconnection or the like does not occur in the opposing electrode formed on the upper layer of the thick insulating film, in an active matrix display device, first, a bank layer composed of a resist film is formed along data lines and scanning lines, and by depositing an opposing electrode of a thin film luminescent element on the upper layer side of the bank layer, capacitance that parasitizes the data lines can be suppressed. Additionally, a discontinuities portion is formed in the bank layer. Since the discontinuities portion is a planar section which does not have a step due to the bank layer, disconnection of the opposing electrode does not occur at this section. When an organic semiconductor film is formed by an ink jet process, a liquid material discharged from an ink jet head is blocked by the bank layer.

There is provided a liquid level detection apparatus for detecting the level of a liquid, including a pair of first electrodes, a pair of second electrodes arranged at a different height to that of the first electrodes, a pair of electrode leads having respective ends connected with the first electrodes and sandwiching therebetween the second electrodes, a grounding unit that changes, between a current-carrying state and an open state, a second electrode current bypass from the second electrodes to a ground line, a first electrode capacitance measurement unit that measures a first electrode capacitance between the first electrodes, with the second electrode current bypass set in the current-carrying state to establish a connection from the second electrodes to the ground line, and a level determination unit that determines the liquid level based on the first electrode capacitance between the first electrodes and a second electrode capacitance between the second electrodes.

A multilayer capacitor array achieves a high ESR because terminal conductors to which internal electrodes in capacitance sections are connected in parallel are connected in series through internal electrodes in ESR control sections to external electrodes. Since in the multilayer capacitor array the internal electrodes extend as far as a boundary between capacitor element portions, electrostriction occurs in an entire laminate including a region near the boundary between the capacitor element portions, with application of a voltage from the outside. Therefore, concentration of stress due to electrostriction is avoided, so as to suppress occurrence of cracking or the like.

An enclosure (4) for electrical apparatus (6) has a sealable outlet (8) for partially evacuating the enclosure and a sealable inlet (9)for partially filling the enclosure with a liquid (7) having a vapor pressure at operating temperatures of the apparatus suitable to enhance electrical isolation of the electrical apparatus and suitable to provide convective cooling of the electrical apparatus. The vapor preferably provides a voltage hold-off sufficiently high for operating voltages of the electrical apparatus and has a relative permittivity sufficiently low to prevent stray capacitance in the electrical apparatus above a predetermined limit.

A display device is disclosed. The display device has a first substrate having a thin film transistor connected to a pixel electrode. Further, the display device has a second substrate opposed to the first substrate and having a resin black matrix.

A thin film transistor (TFT) array substrate and a manufacturing method thereof are provided. The TFT array substrate may include a gate line disposed on a substrate and including a gate line and a gate electrode, an oxide semiconductor layer pattern disposed on the gate electrode, a data line disposed on the oxide semiconductor layer pattern and including a source electrode and a drain electrode of a thin film transistor (TFT) together with the gate electrode, and a data line extending in a direction intersecting the gate line, and etch stop patterns disposed at an area where the TFT is formed between the source / drain electrodes and the oxide semiconductor layer pattern and at an area where the gate line and the data line overlap each other between the gate line and the data line.