3results about How to "Improve failure analysis efficiency" patented technology

This invention provides a method and system for compressing power messages, relating to the field of power system control technology. The method includes: acquiring power messages via a first FPGA; timestamping the acquired power messages; caching the timestamped messages in a first shared memory; extracting messages from the first shared memory; parsing the messages according to their type and classifying and storing them in a second shared memory; extracting messages from the second shared memory by control block using a second FPGA; compressing the compressed packages corresponding to the control blocks; storing the compressed packages in a third shared memory; packaging and secondary compression according to a set time period; generating a total compressed package for that time period; and storing it on an SSD for dual-disk storage. This invention effectively reduces the storage space requirements for historical messages, improves the storage time of historical messages, and solves the problem of frequent failures in storing historical messages for post-event analysis of power systems.

This invention provides a failure analysis method for semiconductor structures, applicable to the field of semiconductor technology. Specifically, it addresses a certain thin-film failure problem in semiconductor samples with thin-film structures made of low-k dielectric materials. By modifying conventional imaging conditions in existing technologies to TEM imaging conditions with a large aperture and a CL1 condenser lens stop, while extending the irradiation time, the high-voltage irradiation energy emitted by the TEM can be used to raise the temperature of the FIB sample. This temperature increase causes surface contraction and tension in the low-k dielectric thin-film structure, amplifying the problem of poor film adhesion. This solves the problem that conventional imaging conditions in existing technologies cannot detect the relatively weak thin-film interface failures in FIB samples, ultimately improving the efficiency of semiconductor structure failure analysis.

This invention relates to a failure analysis fault point prediction method and system, belonging to the field of failure analysis technology, and solves the problem of low efficiency in existing failure analysis methods. The method includes constructing diagnostic sample sets for each testing process and training their respective basic classification models; obtaining the yield rate of fault points based on historical maintenance records, and using cluster analysis to identify normal points within the fault points, and statistically calculating the failure probability of normal points; adjusting the order of each testing step in each testing process based on the failure probability of normal points; obtaining the basic classification model for the corresponding testing process based on the latest diagnostic data of the assembly to be tested; if the accuracy of the current basic classification model is higher than a threshold, inputting the latest diagnostic data into the current basic classification model to predict the fault point; otherwise, obtaining the fault point based on the adjusted order of each testing step in the corresponding testing process and the obtained actual test values. This significantly improves the efficiency of failure analysis.