5 results about "Composite Sequence" patented technology

This invention discloses a composite sequence forced and logical association control method, system, and electronic device for die-casting machines, relating to the field of die-casting machine testing technology. The invention collects multi-source operating data from the die-casting machine and, based on this data and pre-set process rules, determines the process state of the die-casting machine. It acquires a pre-stored forced test sequence and generates corresponding test instructions. The forced test sequence includes trigger conditions and forced steps arranged in a logical order. During the operation of the die-casting machine, it monitors in real time whether the trigger conditions are met. If met, the test instructions are executed according to the timing logic of the forced steps. Simultaneously, it continuously monitors the process state and die-casting machine safety parameters, and controls the interruption and reset of the test instructions based on the monitoring results. This method supports repeatable and safe simulation and verification of complex operating conditions or occasional faults, improving the testing efficiency of the die-casting machine control system.

The invention relates to the technical field of power system automation, and particularly discloses a power network fault early warning method based on a large model, and the method comprises the steps: directly mapping the data of a high-frequency power sensor into a time sequence soft prompt vector which can be understood by the large model through a lightweight encoder and a linear projection technology; deep alignment of continuous signals and discrete semantics is realized, and information loss and efficiency bottleneck caused by numerical textualization are avoided. And then, directionally retrieving an operation and maintenance knowledge base by using the soft prompt vector, introducing a cross-modal affinity matrix to construct a semantic gating mechanism, dynamically screening and enhancing retrieved key knowledge fragments according to real-time waveform characteristics, and automatically inhibiting redundant text noise irrelevant to the current working condition. And finally, deep attention interaction and reasoning are performed on a composite sequence formed by an instruction, enhanced knowledge and soft prompt through a large model, a control signal containing fault classification and disposal suggestions is output, and real-time accurate early warning considering high-frequency signal sensitivity and expert knowledge logicality is realized.

This invention discloses a method and system for quantitatively characterizing the equivalent fault positive-sequence impedance of a new energy grid-connected converter station. First, an equivalent composite sequence network of the system is established by combining the fault ride-through control strategy of the grid-connected converter and the boundary conditions corresponding to different fault types. Then, combining the weak feeder characteristics of the converter system and the topology of the fault composite sequence network, the expression for the positive-sequence voltage at the fault point is derived, and further, the expression for the positive-sequence voltage at the converter station bus is derived. The amplitude and phase changes of the positive-sequence voltage on the converter station bus side under different fault scenarios are studied. Based on the amplitude and phase changes of the positive-sequence voltage on the converter station bus side, the equivalent fault positive-sequence impedance of the converter system corresponding to different fault types is calculated, achieving a certain degree of quantitative characterization of the equivalent positive-sequence impedance of the converter system. This can provide theoretical guidance for the quantitative characterization of converter system fault characteristics, adaptive analysis of protection, and the formulation of new protection principles.

The invention discloses a single-chain multiplexing high-resolution TDC design method and system based on an FPGA and a medium, and the method comprises the steps: carrying out the specific signal configuration of a Carry4 module in a single tap delay chain, and converting a single jump edge of a tested pulse signal into a composite waveform signal containing four jump edges in the chain; sampling the waveform by using a global clock to obtain a composite sequence; the method comprises the following steps: dividing a sequence into two subsequences by adopting a sliding window method, coding two one-hot codes from each subsequence by adopting a neighborhood detection method, and converting to obtain four initial fine count values; and finally, a high-precision fine counting result is obtained through fusion. The method has the advantages that multiple times of multiplexing of a single delay chain is innovatively achieved, consumption of hardware logic resources such as a Carry4 module and a trigger is greatly reduced while the high resolution of an equivalent multi-chain averaging method is achieved, and integration with other functional modules in an FPGA is facilitated.

A method of detecting a fault in a protected line is disclosed. The method may comprise determining a positive sequence power, a negative sequence power and a zero sequence power for a positive sequence, and a negative sequence and a zero sequence, respectively, of power in the protected line. It is determined whether or not a criterion is fulfilled, based on an expression of composite sequence power. If it is determined that the criterion is fulfilled, then a fault is determined to have been detected on the protected line. The method may further comprise determining a delta value of the composite sequence power as a difference between a present composite sequence power value and a previous composite sequence power value. This difference may be determined as a difference between active power parts and a difference between reactive power parts.