4 results about "High density packaging" patented technology

The invention relates to a universal interposer with diagonal vias for testing integrated circuit devices. High density packaging of multiple semiconductor devices results in a very large package that is highly required for reliable testing. Due to the differential coefficient of thermal expansion of the attached parts, the manufacturing process may result in defects such as deformation. The loss of flatness causes a problem to reliable connection in a test environment, resulting in frequent wear of a test socket. A new mode for reducing the connection uncertainty provides higher reliability, and the downtime of maintenance is greatly reduced.

The utility model provides an aviation high density packaging shell and radiating assembly, relate to packaging shell technical field, including shell connecting heat conduction seat, radiating fin group, heat pipe heat conduction structure, the radiating assembly that adopts is through shell connecting heat conduction seat fastly with the heat of electronic device in packaging shell generation heat pipe heat conduction structure heated end is oriented, and heat pipe heat conduction structure passes through the heat of heat pipe own characteristic transmission to radiating fin group place, and radiating is carried out through radiating fin group, and the heat dissipation effect of better realization is met the heat dissipation demand of packaging electronic device in aviation field through the auxiliary heat dissipation of heat conduction shell and heat conduction inner shell of packaging shell.

Semiconductor devices and methods of manufacturing the same are described. Transistors are fabricated using a standard process flow. A via opening extending from the top surface of the substrate to a bottom surface of the wafer device is formed, thus allowing nano TSV for high density packaging, as well as connecting the device to the backside power rail. A metal is deposited in the via opening, and the bottom surface of the wafer device is bound to a bonding wafer. The substrate is optionally thinned, and a contact electrically connected to the metal is formed.

High density packaging of multiple semiconductor devices creates very large packages that are demanding to test reliably. The fabrication process causes imperfections such as distortion due to differential thermal expansion rates of attached parts. The loss of flatness creates a problem for reliable connectivity in a test environment leading to frequent wear in test receptacles. A novel approach to mitigate connection uncertainties offers greater reliability with much reduced down time for maintenance.