120 results about "High density packaging" patented technology

Various components and methods related to electrical connectors are disclosed. The electrical connectors can be configured to receive a plurality of cables. The electrical connectors can be configured to accommodate a plurality of cables so as to provide a high density packaging within each of the pair of electrical connectors. In order to provide appropriate shielding against electric flux and to reduce noise, each of the plurality of cables can be retained within a genderless insert that can be inserted through each of the pair of electrical connectors. Each of the genderless inserts can include an engagement end that allows the interconnection of the cables retained within the pair of electrical connectors. In some examples, the engagement end of each of the genderless inserts includes both a male and female component.

Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.

In a semiconductor chip having electrodes formed on the top surface, and electrodes or an insulation layer formed on the back surface, the top-surface electrodes are loop-connected with the back-surface electrodes by wire bonding, or, the top-surface electrodes are connected with the back-surface electrodes or an insulation layer by conductive clip, or by deposited conductive materials. The semiconductor chips thus produced are stacked, and wires, conductive clips, or conductive materials are connected and fixed to each other to produce a stacked semiconductor device in which semiconductor chips of the same size are densely packaged. Thus, a semiconductor device is provided which enables high-density packaging of semiconductor chips even of the same size.

A subject for the invention is to improve the cycle characteristics of a high-capacity secondary battery containing an active material packed at a high density, by using a particulate active material having a low aspect ratio. The invention relates to a nonaqueous-electrolyte secondary battery comprising a negative electrode and a positive electrode each capable of occluding/releasing lithium, a separator, and a nonaqueous electrolyte solution comprising a nonaqueous solvent and a lithium salt, characterized in that the separator comprises a porous film made of a thermoplastic resin containing an inorganic filler, and at least either of the following is satisfied: the active material contained in the negative electrode is a particulate active material having an aspect ratio of from 1.02 to 3; and the active material contained in the positive electrode is a particulate active material having an aspect ratio of from 1.02 to 2.2.

A substrate for packaging a storage or server system may include one or more sections of the substrate configured to hold a two-dimensional array of disk drives. Another section of this substrate may be configured to hold circuitry for accessing the array of disk drives. This circuitry may include one or more processors. The substrate also includes a first plurality of ribs positioned in the first access of the substrate. The first plurality of ribs separate the sections from one another. The section configured to hold the control circuitry may also be configured to hold one or more power supplies for supplying power to the array of disk drives and control circuitry. This section, as well as other sections, may be divided in two by one or more additional ribs in a transverse direction. The substrate may be configured to be mounted in a cage or rack and may include an edge connector at one edge of the substrate to provide electrical connectivity to a back plane in the cage or rack. A lateral protrusion may extend along each parallel edge of the substrate for mounting the substrate in the cage or rack by sliding the substrate into the cage or rack.

A capacitor capable of being incorporated into a packaging substrate, characterized in that the capacitor comprises a high-dielectric-constant layer, and an upper electrode layer and a lower electrode layer sandwiching the high-dielectric-constant layer from the upper side and the lower side. A packaging substrate containing the capacitor, and a method for producing the same are also provided.

The invention relates to a packaging part with double-row pins and four flat and pin-free surfaces and a production method thereof. The packaging part comprises a lead frame carrier, an IC chip, a bonding pad, inner lead pins, bonding lines and a plastic packaging body and is characterized in that the inner lead pins are arranged into two rows, i.e. the inner lead pin (4) and the inner lead pin (5), each pair of lead pins are connected together, a groove is arranged in the middle of the connected pins, the bonding pads are respectively connected with the inner lead pin (4) and the inner lead pin (5) through the bonding lines, an anti-spilling groove is arranged at the bottom of the carrier, and grooves are arranged at the bottoms of the inner lead pins. The packaging part is processed and produced through the processes of reduction, scribing, chip installation, press welding, plastic packaging, electroplating, cutting and the like. The carrier is diminished, the inner lead pins are inwards extended and designed into double rows, and the packaged I/O number is increased, thereby not only markedly saving the cost of plastic packaging materials, but also realizing the thin and miniaturized packaging of portable products, being suitable for multi-pin high-density packaging, and improving the packaging density.

A scalable, flexible, automated radio frequency distribution system (FORFDS) employs fiber optics to eliminate the need for metallic/coaxial type interconnections between onboard and fixed-site radios and antennas. Key elements of the FORFDS may include, for example, 1) electrical to optical conversion (and vice versa) of RF signals, 2) optical switching, 3) automated control and monitoring, including Ethernet interfaces, and 4) high density packaging. The system is compatible with JTRS (2 MHz to 2000 MHz), is scalable and cost effective (no longer in the laboratory or concept high cost ranges), compared with known technologies.

A package comprises a substrate with a plurality of metal tracks, a via hole formed in the substrate, wherein the sidewall of the via hole is partially plated and the via hole is filled with a magnetic material, and a first winding magnetically coupled to the via hole.

An integrated circuit constructed on a folded integrated circuit is described. The folded integrated circuit has a much smaller form-factor than the original (unfolded) circuit and is thus more suitable for use in miniature devices, such as, for example, electronic camera, electronic-film cartridge, cellular telephone, handheld computer, handheld digital music device, portable devices, handheld devices, and the like. In one embodiment, the integrated circuit is folded by thinning an area of the substrate such that the thinned area of the substrate becomes flexible. Conducting traces on the upper surface of the substrate connect an active region on one side of the thinned area to an active region on the other side of the thinned area. The substrate is folded at the thinned area to thereby reduce the size of the substrate. In one embodiment, a heat-sink is inserted between the folds to carry heat away from the substrate.

Copper pillar tin bump on semiconductor chip comprises a copper layer composed on chip and a tin layer entirely wrapping whole outer surface of said copper layer. A method for forming of the copper pillar tin bump on semiconductor chip comprises: composing the first copper layer on said chip; applying photoresist to said first copper layer, exposing and developing a part of said photoresist, composing the copper pillar layer at the developed part of photoresist, composing the upper tin layer, removing said photoresist, removing said the first copper layer except disposing place of copper pillar layer, composing side tin layer. The minute pattern makes it possible to form a high density packaging by reducing a pitch of copper pillar tin bump. Signal delay can be reduced by low electric resistance, and underfill can be easily soaked.

For high density packaging of a semiconductor device, the semiconductor device has a multi-layer substrate, a first-stage chip connected electrically to the multi-layer substrate, other package substrates stacked in three stages on the multi-layer substrate and each connected to an underlying wiring substrate through solder balls, second-, third- and fourth-stage chips electrically connected respectively to the other package substrates, and solder balls provided on the bottom multi-layer substrate. The number of wiring layers in the bottom multi-layer substrate which has a logic chip is larger than that in the package substrates which have memory chips, whereby the semiconductor device can have a wiring layer not used for distribution of wires to the solder balls and wiring lines in the wiring layer can be used for the mounting of another semiconductor element or a passive component to attain high density packaging of the semiconductor device as a stacked type package.

An article includes a mounting substrate, a passive component site on the mounting substrate, and an active component site on the mounting substrate. The article also includes a fluid flow barrier disposed local to the passive component site and spaced apart from the active component site. The fluid flow barrier can be a recess that resists fluid flow thereinto because of surface tension of the fluid when it meets the recess edge. The fluid flow barrier can include a boundary that diverts fluid flow due to the angle of the recess edge as the fluid approaches it. An embodiment also includes a packaging system that includes the article and at least one passive component. An embodiment also includes a method of assembling the article or the packaging system.

The invention relates to a fan-out high-density packaging method, which comprises the following steps of: providing a carrier plate; forming a stripping membrane on the carrier plate; forming protective layers on the stripping membrane; forming a rewiring metal layer in the protective layers; forming wiring packaging layers which are conductive with the rewiring metal layer on the protective layers; forming inversion packaging layers on the wiring packaging layers, wherein the packaging layers are connected electrically and mutually by wiring layers and welding flux salient points; removing the carrier plate and the stripping membrane, so that rewiring metal in a first protective layer is exposed; and forming a metal welded ball on the exposed rewiring metal. Compared with the prior art, the fan-out high-density packaging method has the advantages that: a final packaging product with an integral systemic function instead of a single chip function can be formed, and the resistance and inductance in a system and interference factors among chips are reduced. In addition, a complex multi-layer interconnection structure can be formed, so that the wafer system-level packaging of a higher integration level is realized.

Display packaging constructions incorporating a plastic blister cavity, sandwiched between layers of paperboard material, preferably corrugated paperboard material, are disclosed. Variations of the basic construction include a high-density packaging configuration, display packages having security features for precluding unauthorized access to the interior of the display package, and a reclosable construction to enable the display package to be used as a storage container. When corrugated paperboard is used for the layers, the corrugations may be arranged to extend transversely to one another, to resist warping caused during the heat sealing process. A plastic blister construction is provided, having a forward stabilizing foot, and a rear concavity, for receiving a similar foot from a like blister, for facilitated nested packing together of pluralities of such blisters.

A high density storage device packaging apparatus in which storage devices are oriented to have lateral faces parallel to each other and to edges of a module in which the storage devices are mounted. The storage devices are connected to a board contained in the module by a plug-in action. The board contains a controller to control the operation of the storage devices including the READ and WRITE operations. The RSM is capable of holding a large number of storage devices and capable of being inserted into a cabinet by a plug-in connection. The RSM includes a housing that covers and protects the storage devices and includes air channels to allow the storage devices to cool. The invention provides a solution for high density packaging of the storage devices and allows for easy access to the storage devices and allows for replacement of failed storage devices without disruption of the remainder of storage devices in the RSM or in the cabinet.

The invention relates to a chip-level bottom filling adhesive, which comprises following components by weight percentage: 15 to 50 percent of epoxy resin, 1 to 20 percent of toughening agent, 0.1 to 1 percent of dispersing agent, 0.01 to 1 percent of defoaming agent, 0.8 to 10 percent of cross-linking agent, 0.1 to 0.5 percent of pigment, 40 to 70 percent of filler, 3 to 30 percent of curing agent and 1 to 20 percent of diluting agent. A preparation method of the chip-level bottom filling adhesive comprises the steps that the epoxy resin, toughened resin, the dispersing agent, the defoaming agent, the cross-linking agent and the pigment are weighed according to the proportion, thrown into reaction kettle and mixed to form a homogeneous solution; and afterwards, the filler, the curing agent and the diluting agent are weighed according to the proportion, thrown into the reaction kettle in sequence and evenly mixed with the homogeneous solution, and then the chip-level bottom filling adhesive is obtained. The bottom filling adhesive prepared by adopting the method has the characteristics of low curing shrinkage rate, high reliability, and the like, simultaneously satisfies the requirement of low radioactivity and is suitable for primary high-density packaging of memory chips.

The invention discloses bottom filling glue for packaging an inverted chip type semiconductor, which is prepared from the following raw materials in percentage by weight: 5.8-59 percent of liquid epoxy resin, 2-10 percent of rubber toughening agent, 5.8-59 percent of modified organic silicon resin, 0.5-14.8 percent of multifunctional epoxy resin, 1.5-10.5 percent of epoxy diluent, 0.5-14.8 percent of aromatic amine curing agent, 1.1-10.8 percent of silane coupling agent, 20-59 percent of silicon micropowder and 0-6 percent of pigment. The invention has the advantages of low viscosity, proper flow property, no defect, no bubble and good heat resistance of resin condensate, low thermal expansion coefficient, low modulus, small internal stress, less warping degree, high bonding strength, low halogen content and high insulating performance, can maintain favorable bonding reliability and curing performance during thermal cycling treatment and improve the seal performance and the operating performance of the surface of a silicon wafer containing photosensitive polyimide and a silicon nitride film, can be widely used for the technical field of inverted chip packaging and is especially suitable for the field of high-end devices in a Flip-chip process and high-density packaging.

An enhanced heat dissipation device to extract heat from an integrated circuit device includes a thermally conductive core having upper and lower outer surface areas. The device further includes a first array of radially extending pin fin structures. The first array is thermally coupled to the upper surface area such that a cooling medium introduced around the core and the first array creates an omni-directional flow around the first array and the core to enhance heat dissipation from the integrated circuit device. The core including the first array and the lower surface area are of sufficient size to allow components on a motherboard to encroach onto the integrated circuit device when the heat dissipation device is mounted onto the integrated circuit device.

A semiconductor device mounting board in which high density packaging and fining can be realized in response to smaller pitches while ensuring excellent reliability of package by improving a conventional wiring board, its producing method and inspecting method, and a semiconductor package. The semiconductor device mounting board in characterized by comprising a wiring structure film consisting of an insulation layer and a wiring layer, a first electrode pattern provided on one surface of the wiring structure film such that at least the side circumference thereof touches the insulation layer but at least the lower surface thereof does not touch the insulation layer and the surface of the insulation layer provided with the first electrode pattern is coplanar with the lower surface of the first electrode pattern, a second electrode pattern formed on the surface opposite to the first electrode pattern, an insulator film provided with an opening pattern being confined in the first electrode pattern, and a metal support provided on the surface of the insulator film.