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37results about How to "Memory efficient" patented technology
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Scratch pad block
ActiveUS7315916B2Improve performanceWrite efficientlyMemory architecture accessing/allocationRead-only memoriesHigh densityHigh velocity
In a memory array having a minimum unit of erase of a block, a scratch pad block is used to store data that is later written to another block. The data may be written to the scratch pad block with a low degree of parallelism and later written to another location with a high degree of parallelism so that it is stored with high density. Data may be temporarily stored in the scratch pad block until it can be more efficiently stored elsewhere. This may be when some other data is received. Unrelated data may be stored in the same page of a scratch pad block.
Owner:SANDISK TECH LLC
Remoting features
InactiveUS7155728B1To offer comfortEasy to produceProgram controlEntry pointUniform resource identifier
A system and method that provides remoting services in a distributed object system is provided. The system includes a remote object monitor and a remote object manipulator. The remote object monitor can provide a human readable reference to a remote object, where the human readable reference is a URL (Uniform Resource Locator) and can include protocol information, protocol data, an application name and an object URI (Uniform Resource Identifier). The remote object monitor can also provide metadata concerning a remote object, where the metadata can include information concerning interfaces implemented by a remote object, the type of a remote object, the class hierarchy of a remote object, methods implemented by a remote object, properties implemented by a remote object and attributes implemented by a remote object. The remote object monitor can also provide entry points and code interception for custom attribute based activation processing that can be performed before, after and / or substantially in parallel with non-attribute code associated with a remote object. The remote object monitor can also monitor and / or control the lifetime of a remote object, using, for example, a lease manager. The remote object manipulator can also update metadata concerning a remote object and can control the lifetime of a remote object via a lease manager, for example.
Owner:MICROSOFT TECH LICENSING LLC
Memory efficient use of dynamic data structures used to manage sparsely accessed data
ActiveUS8819386B1LessEfficient data structureMemory adressing/allocation/relocationMicro-instruction address formationShardDynamic data structures
When a dynamic data structure is used for managing sparsely accessed data stored in memory of a digital computer, pages of the memory are dynamically allocated and de-allocated to respective portions of the dynamic data structure so that the pages become distributed over the portions of the dynamic data structure and the de-allocated pages include free pages that are mapped in the dynamic data structure and free pages that are not mapped in the dynamic data structure. To reduce memory fragmentation and recover memory, upon de-allocating a page of memory from a portion of the data structure, a determination is made whether or not to un-map the de-allocated page from the portion of the dynamic data structure so that un-mapping of the de-allocated page has a probability that is the inverse of a superlinear function of the number of allocated pages in the portion of the dynamic data structure.
Owner:EMC IP HLDG CO LLC
Method and apparatus for reducing video data memory in converting VGA signals to TV signals
InactiveUS6141055AEfficient reuseReduce memory capacityTelevision system detailsColor signal processing circuitsComputer architectureFrame time
It is disclosed herein that a system for reducing video data memory in VGA-to-TV converters that convert computer video signals to TV compliant signals for display on regular TV screens. By closely tracking two pointers, one being a write pointer responsible for writing incoming video data into the video data memory and the other being a read pointer responsible for reading out the stored video data in the video data memory, the memory is efficiently used for buffering the video data. To ensure that the read pointer always retrieves the valid video data at its own speed, an address monitoring process is provided to monitor the address difference between the write pointer and the read pointer. When the monitoring process detects that the read pointer may soon surpass the write pointer, a control process is placed on the write pointer to prevent the read pointer from passing over the write pointer. Depending on the speed difference between the write and read pointers, the writer pointer is either paused for a frame time or assigned to a secondary write pointer that writes data into the memory just visited by the read pointer. The efficient use of the memory makes it possible to reduce the memory capacity to a minimum so as to reduce the cost of manufacturing the converters.
Owner:ALTECH INT CORP
Efficient buffer allocation for current and predicted active speakers in voice conferencing systems
InactiveUS20050025073A1Reduce lossesMemory efficientSpecial service provision for substationMultiplex system selection arrangementsLoudspeakerSpeech sound
A method and computer program product allows for the efficient allocation of buffers (e.g., first-in first-out (FIFO) queues) for current and predicted active speakers in voice conferencing systems. The method and computer program product, implemented by a server hosting an audio conference for a plurality of speakers, minimizes the loss of audio data for speakers as they switch from “non-active” to “active” status. This is accomplished by employing a set of active speaker buffers and a set of predicted active speaker buffers. The predicted active speaker buffers maintain a collection of the most recent x packets or m milliseconds of “non-active” speaker audio data, and transfer a portion of the data from the predicted active speaker buffers to the active speaker buffers as speakers become “active” speakers. The x packets or m milliseconds of stored “non-active” speaker audio data can be used only up to a pre-determined jitter buffer fill-level in order to avoid introducing additional audio packet delivery delay to participants of the conference.
Owner:KWAN KATHERINE WANG
Method and System for Through-the-Wall Radar Imaging
ActiveUS20170023673A1Memory efficientImprove qualityRadio wave reradiation/reflectionComputer visionRadar imaging
A method and system for generating an image of a scene behind a wall, wherein the scene is represented as a grid, by first transmitting a radar pulse through the wall using a transmitter and receiving a set of echoes corresponding to the radar pulse being reflected by the scene in a receiver at a known location. Based on the location, an imaging operator that relates the set of echoes to the grid is determined. Using the imaging operator, a sparse delay kernel that matches a response of a current image to a similar response in the set of echoes is determined. Then, the current image is updated, based on the set of echoes, the imaging operator, and the sparse delay kernel. The transmitting, the receiving, the determining, the obtaining, and the updating steps are repeated for different locations until a termination condition is reached.
Owner:MITSUBISHI ELECTRIC RES LAB INC
Interleaving apparatus and method for a communication system
ActiveUS6910110B2More memory efficientMemory efficientError preventionCode conversionData bitsLeast significant bit
An interleaving apparatus and method for a communication system which can be applied to determine a new interleaver size N′=2m×(j+1) and addresses of 0 to N′−1, if a given interleaver size N is larger than 2m×j and smaller than 2m×(j+1), where m represents a first parameter indicating a number of consecutive zero bits from a least significant bit (LSB) to a most significant bit (MSB), and j represents a second parameter corresponding to a decimal value other than said consecutive zero bits. The interleaving apparatus and method sequentially stores N input data bits in an interleaver memory with the new interleaver size N′ from an address 0 to an address N−1. The interleaving apparatus and method then executes a Partial Bit Reversal(PBRO)-interleaving the memory with the new interleaver size N′, and reads data from the memory by deleting addresses corresponding to addresses of N to N′−1 of the memory before interleaving.
Owner:SAMSUNG ELECTRONICS CO LTD
Method and apparatus for using a color table scheme for displaying information on either color or monochrome display
InactiveUS7075555B1Easy to debugEffective mechanismCathode-ray tube indicatorsDigital output to display deviceObject basedOperational system
A method and system of determining the screen capability and rendering the appropriate display attribute is herein described. The present invention performs this task by using a color table, which contains a list of object types and a corresponding list of display attributes. The application program obtains the correct display attribute for the object by calling the color table, giving it an identifier of the object. The color table is indexed by the identifier of the object and a screen capability flag that is obtained, in one embodiment, from the operating system. The color table provides the display attribute for the specified object based on the screen capability flag. Advantageously, the application program does not need to know the computer's display capability. Furthermore, the application program needs only one piece of computer code, regardless of the number of display capabilities which are possible. Thus, memory space in the palmtop is conserved. In another embodiment of the present invention, the application program is allowed to modify the default values of the display attributes in the color table. Thus, an application program could use its own color to display an object if the default color is undesirable.
Owner:ACCESS
Image expansion and display method, image expansion and display device, and program for image expansion and display
InactiveUS20050008236A1Large capacityHigh speed displayTelevision system detailsGeometric image transformationInformation analysisDisplay device
A header information analysis section analyzes header information of a compressed image file and reads an original image size while comparing the read original image size and an image size required for display and performing an operation of a size ratio. A JPEG expansion section expands image data of the image file by MCU. A resizing section magnifies or reduces by MCU the image data expanded by the JPEG expansion section according to the size ratio obtained by the header information analysis section and transfers the magnified or reduced data to a display frame memory.
Owner:PANASONIC CORP
Multi-domain controller virtual machine data communication method and device based on vehicle-mounted Ethernet
ActiveCN112235210AFlexible schedulingFlexible data communicationData switching networksIn vehicleEngineering
The invention provides a multi-domain controller virtual machine data communication method and device based on a vehicle-mounted Ethernet, and the device comprises a first multi-domain controller anda second multi-domain controller; the multi-domain controller comprises a hardware platform and a virtual machine manager located on the hardware platform, and a virtual machine operates on the virtual machine manager; the first multi-domain controller acquires data from a chassis domain and a power domain and analyzes and processes the data through a plurality of virtual machines; the second multi-domain controller acquires data from the intelligent driving domain, the information entertainment domain and the vehicle body domain and analyzes and processes the data through a plurality of virtual machines, and the virtual machines on the multi-domain controller communicate in a shared memory mode of a dynamic adjustable storage space. According to the method, the data between domains can beoperated independently and safely isolated, the efficiency can be improved, and the cost can be reduced.
Owner:SHANGHAI HEQIAN ELECTRONICS TECH CO LTD
Area efficient memory architecture with decoder self test and debug capability
ActiveUS20070002649A1Reduce test timeNegligible area overheadElectronic circuit testingError detection/correctionAccess timeTest facility
An integrated test device reduces external wiring congestion to a memory. The integrated test device provides for separate decoder testing and debugging to find specific errors in the memory. The device also helps in reducing the complexity of the test of external BIST. Furthermore, the number of clock cycles required for the decoder testing for an N-address memory is reduced from 4N cycles to N clock cycles. Additionally, the access time for the memory is reduced as the test device is used as a pipelining device in normal operation mode.
Owner:STMICROELECTRONICS PVT LTD
Memory efficient streamlined transmitter with a multiple instance hybrid ARQ
ActiveUS20060206777A1Memory efficientError prevention/detection by using return channelData representation error detection/correctionMultiplexerBit pairing
An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate an output signal in response to a first intermediate signal and a second intermediate signal. The second intermediate signal comprises a series of bit pairs. The second circuit comprises a first and a second encoder and may be configured to generate the second intermediate signal in response to a third intermediate signal. The third circuit may be configured to generate the first intermediate signal and the third intermediate signal in response to a first address signal and a second address signal. The third circuit comprises a first multiplexer and a second multiplexer.
Owner:APPLE INC
Behavioral model based on short and long range event correlations in system traces
ActiveUS20160239596A1Efficient representationSure easyComputer security arrangementsDesign optimisation/simulationComputerized systemComputer science
A method of generating a behavioral model of a computer system. A processor partitions a system log of process events into a plurality of strands sharing common characteristics. The processor selects attributes from the strands and generates first distinct n-grams that include attributes from successive events within a strand. The processor generates a first plurality of n-gram groups, each including a plurality of the first distinct n-grams in which a first one of the plurality of first distinct n-grams coexists in a strand also containing a second one of the plurality of first distinct n-grams. The processor generates a first plurality of n-gram group arrangements, each containing a plurality of n-gram groups, and each of the n-gram groups included, in combination, in at least one strand, and the behavioral model containing the first distinct n-grams, the first plurality of n-gram groups, and the first plurality of n-gram group arrangements.
Owner:IBM CORP
Resource management method and system for large-scale distributed deep learning
PendingCN111858072AReduce memory consumptionAddress the double pressureResource allocationNeural learning methodsParallel computingData access
The invention discloses a resource management method and system for large-scale distributed deep learning, and the method and system achieve the memory resource optimization management of parameters and gradient intermediate data during the training operation of a neural network, and guarantee the reasonable configuration of distributed communication bandwidth resources. Cross-layer memory reuse is realized again, intermediate data required by iterative computation and sparse communication are migrated into a CPU main memory and then migrated back as required, and interlayer memory consumptionis reduced; on the basis of reasonable migration of CPU-GPU data, independence of intra-layer memory reuse, intra-layer calculation mining and memory access operation is achieved, and intra-layer memory consumption is reduced as much as possible. Distributed parameter communication optimization is realized while efficient utilization of memory resources is ensured. Data access in the distributedparameter updating stage is reasonably redirected, a CPU main memory serves as a mirror image access area, the data access to parameters and gradients is completed, and the problems of gradient data missing and parameter writing border crossing are solved.
Owner:HUAZHONG UNIV OF SCI & TECH
Subset transform interleaver
ActiveUS20120242518A1Reduce complexityMemory efficientCode conversionCoding detailsCoding blockTheoretical computer science
Digital communications interleavers re-order the bits of a data coding block in a way that can be described by a table of indices that map the original order to the interleaved order. Conventional interleavers include index table interleavers, which store an index table ahead of operation and algorithmic Interleavers, which generate the indices during operation.Described herein are a new class of interleavers: Subset Transform Interleavers. A subset of generator outputs is selected and processed to create the interleaver indices. The selection is determined apriori and the selection results are stored in a Subset Usage Table. During operation, the generator is operated again and the Subset Usage Table entries determine which generator outputs are used. The generator may be a pseudo-random number generator. Implementations can use an Indexes Remaining Table, which can additionally be manipulated during operation such that it returns to an initialized state after each block interleaving process.
Owner:VIASAT INC
Area efficient memory architecture with decoder self test and debug capability
ActiveUS8046655B2Reliably detect and segregateShorten test timeElectronic circuit testingError detection/correctionAccess timeOperation mode
An integrated test device reduces external wiring congestion to a memory. The integrated test device provides for separate decoder testing and debugging to find specific errors in the memory. The device also helps in reducing the complexity of the test of external BIST. Furthermore, the number of clock cycles required for the decoder testing for an N-address memory is reduced from 4N cycles to N clock cycles. Additionally, the access time for the memory is reduced as the test device is used as a pipelining device in normal operation mode.
Owner:STMICROELECTRONICS PVT LTD
Method, system, and computer program product for managing a re-usable resource with linked list groups
InactiveUS6976021B2Memory efficientData processing applicationsMemory adressing/allocation/relocationHash tableDatabase
A pool of integers is managed by dividing the pool of integers into groups and initializing, in memory, doubly linked lists related to the groups on an as needed basis in response to requests to allocate integers. If an initialized group of integers no longer includes any allocated integers, the doubly linked list related to the group is deleted from memory. Memory locations of the group-specific doubly linked lists are identified by a hash table that includes a unique hash table pointer for each one of the groups. Each element of the doubly linked list includes a next pointer for identifying a next element and a previous pointer for identifying a previous element. A specific free integer can be allocated in an order of one, O(1), operation by indexing into the linked list and utilizing the next and previous pointers of the linked list element to remove the linked list element from the linked list.
Owner:RIVERSTONE NETWORKS
Readout arrangement for an image sensor, image sensor system and method for reading out an image sensor
ActiveUS20190342513A1Reduce data volumeImprove system performanceTelevision system detailsColor television detailsAnalog signalComputer science
A readout arrangement for an image sensor is configured to receive from a plurality of column leads of the image sensor in parallel a plurality of image sensor analog signals describing in an analog manner brightness values detected by the image sensor. The readout arrangement is configured to select which subset of a plurality of analog values represented by the image sensor analog signals or based on the image sensor analog signals is to be stored in an analog memory for further processing, and to cause storage of the selected analog values in the analog memory, or to store the selected analog values in the analog memory.
Owner:FRAUNHOFER GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG EV
Location estimation in a communication network
ActiveUS20160349351A1Memory efficientAccurate locationPosition fixationUsing reradiationCell specificEvent data
A method, apparatus and computer program are provided for estimating a characteristic static location of a user equipment in a wireless communication network comprising a plurality of network nodes for transmitting radio signals. Each network node has an associated cell corresponding to a predicted geographical coverage area of a corresponding transmitted radio signal. Location event data for the user equipment provides a cell-specific location for the user equipment at a point in time. A plurality of event frequencies is determined for the user equipment, each corresponding to a cumulative number of received location events locating the user equipment in a respective cell / sector in a given time interval. A characteristic static location is calculated using a combined measure of at least two non-zero values of the plurality of event frequencies corresponding respectively to at least two different cells or sectors.
Owner:VODAFONE IP LICENSING
Gaussian mixture model based approximation of continuous belief distributions
ActiveUS20210279955A1Improve fidelityIncreasing fidelity lowerNavigational calculation instrumentsCharacter and pattern recognitionAlgorithmComputer science
A system and method to generate perceptual models of the environment that optimally handle the variation in clutter and provide a multiresolution and multi-fidelity representation of the environment is described. The system and method is able to capture inherent structural dependencies, thereby allowing efficient and precise inferences to be drawn. The approach employs a hierarchy of Gaussian Mixtures to approximate the underlying spatial distribution.
Owner:CARNEGIE MELLON UNIV
Video-based system and method for parking occupancy detection
ActiveUS9672434B2Reduce illumination variationComputationallyImage enhancementIndication of parksing free spacesParking spaceSpacetime
A spatiotemporal system and method for parking occupancy detection. The system can generally include suitable image acquisition, processing, transmission and data storage devices configured to carry out the method which includes generating and processing spatiotemporal images to detect the presence of an object in a region of interest, such as a vehicle in a parking stall.
Owner:CONDUENT BUSINESS SERVICES LLC
Behavioral model based on short and long range event correlations in system traces
ActiveUS10380340B2Resist attackLittle usePlatform integrity maintainanceMarketingComputerized systemComputer science
Owner:INT BUSINESS MASCH CORP
Behavioral model based on short and long range event correlations in system traces
ActiveUS10372906B2Resist attackLittle usePlatform integrity maintainanceMarketingComputerized systemComputer science
A method of generating a behavioral model of a computer system. A processor partitions a system log of process events into a plurality of strands sharing common characteristics. The processor selects attributes from the strands and generates first distinct n-grams that include attributes from successive events within a strand. The processor generates a first plurality of n-gram groups, each including a plurality of the first distinct n-grams in which a first one of the plurality of first distinct n-grams coexists in a strand also containing a second one of the plurality of first distinct n-grams. The processor generates a first plurality of n-gram group arrangements, each containing a plurality of n-gram groups, and each of the n-gram groups included, in combination, in at least one strand, and the behavioral model containing the first distinct n-grams, the first plurality of n-gram groups, and the first plurality of n-gram group arrangements.
Owner:INT BUSINESS MASCH CORP
Method and system for through-the-wall radar imaging
ActiveUS9915730B2Memory efficientQuality improvementRadio wave reradiation/reflectionRadar imagingComputer vision
A method and system for generating an image of a scene behind a wall, wherein the scene is represented as a grid, by first transmitting a radar pulse through the wall using a transmitter and receiving a set of echoes corresponding to the radar pulse being reflected by the scene in a receiver at a known location. Based on the location, an imaging operator that relates the set of echoes to the grid is determined. Using the imaging operator, a sparse delay kernel that matches a response of a current image to a similar response in the set of echoes is determined. Then, the current image is updated, based on the set of echoes, the imaging operator, and the sparse delay kernel. The transmitting, the receiving, the determining, the obtaining, and the updating steps are repeated for different locations until a termination condition is reached.
Owner:MITSUBISHI ELECTRIC RES LAB INC
Word fusion memorizing method and system based on multi-dimensional game mechanism
PendingCN114528808AImprove memory depthMemory efficientNatural language data processingElectrical appliancesEngineeringArtificial intelligence
The invention discloses a word fusion memorizing method and system based on a multi-dimensional game mechanism. The method comprises the steps of obtaining a learning stage and a target selected by a user; arranging horizontal tests of multiple angles for the user according to the learning stage and the target; setting a daily learning task amount according to a horizontal test result, and pushing a learning plan every day; words are extracted from the current day to-be-reviewed queue and the new word library, and daily basic training is carried out; acquiring the learning state of each word of the user, and arranging the next review time of each word according to the learning state of each word; generating a plurality of exploration levels according to words learned on that day, and obtaining a word consolidation result of the user in a gamification form; matching social themes according to the learning words on that day, matching other users with consistent learning progress by using a recommendation algorithm, and entering a social application. According to the method, memory is deepened in a multi-dimensional gamification answer form, overdue learning conditions of the user are considered, the review interval is adjusted, and the review time is reasonably arranged.
Owner:盘达学趣(武汉)科技有限公司
Image superposition display method for automobile full-liquid-crystal instrument
ActiveCN110347391AOptimize bandwidth overheadThe effect is positive and obviousSoftware engineeringMachine execution arrangementsVideo memoryHardware modules
The invention discloses an image superposition display method for an automobile full-liquid-crystal instrument. The method comprises a process of inputting an instruction to an imx6 series microprocessor, a chip comprising an expansion interface glTexDirectVIVMap, and the process of inputting the instruction to the microprocessor comprising a step of storing an instruction code in a memory and a step of inputting the instruction code into the microprocessor for execution. And through an expansion interface glTexDirectVIVMap, an image generated through instrument software and an image from far-end central control entertainment equipment of the LVDS in video cable are displayed in a video memory binding mode. Based on a QNX operating system on imx6 series chips, hardware modules of GPUs in the chips are fully utilized, an imx6 special expansion interface is adopted, a video memory binding mode is used for replacing a mode of continuously generating new textures, and bandwidth expenditureof video data frame copying is optimized.
Owner:YANFENG VISTEON ELECTRONICS TECH (SHANGHAI) CO LTD
A bwt-based protocol field reverse analysis system and method
ActiveCN109040081BQuick searchImprove design flexibilityData switching networksHigh level techniquesReverse analysisTheoretical computer science
The invention provides a protocol field reverse analysis system and method based on BWT. Specific suffix index is constructed, so that specific substring matching only needs to be completed once in each alignment process. Moreover, the alignment algorithm based on suffix index is flexible in design, consumes less space in the index stage, and the length of subsequence is variable, protocol fieldscan be quickly identified. After the fixed field is identified, the invention counts the fields with high frequency through a random multi-stream multi-segment matching method, constructs a grammar tree according to the field position and the number of the fields, extracts the field structure, and thus realizes the inverse of the field format. After being classified, the reverse field is used asthe input of the fuzzy test tool, a large number of deformity test cases is sent to the target communication entity, and at the same time, the debugger is combined with the sniffer to carry out abnormal monitoring on the target communication entity, the abnormality is found and analyzed, so as to subsequently improve the safety of the target communication entity.
Owner:HARBIN INST OF TECH AT WEIHAI
Method and apparatus for using a color table scheme for displaying information on either color or monochrome display
InactiveUS20060250406A1Easy to debugMemory efficientCathode-ray tube indicatorsDigital output to display deviceObject basedOperational system
Owner:ACCESS SYSTEMS AMERICAS
Readout arrangement for an image sensor, image sensor system and method for reading out an image sensor
ActiveUS11115613B2Reduce data volumeImprove system performanceTelevision system detailsColor television detailsEngineeringAnalog signal
A readout arrangement for an image sensor is configured to receive from a plurality of column leads of the image sensor in parallel a plurality of image sensor analog signals describing in an analog manner brightness values detected by the image sensor. The readout arrangement is configured to select which subset of a plurality of analog values represented by the image sensor analog signals or based on the image sensor analog signals is to be stored in an analog memory for further processing, and to cause storage of the selected analog values in the analog memory, or to store the selected analog values in the analog memory.
Owner:FRAUNHOFER GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG EV
A teaching aid for learning English words
InactiveCN103824479BEasy to rememberInteresting memoryMechanical appliancesChinese charactersLettering
The invention discloses a training aid for learning English words, The training aid comprises a base and a containing cavity, wherein a training aid shell is arranged on the base; an English display region for holding English letter cards is arranged on the training aid shell; the containing cavity is arranged on the training aid shell, is used for holding Chinese character cards and is communicated with a Chinese character card display region on the training aid shell; an opening and closing device for controlling the Chinese character cards to enter the Chinese character card display region via the containing cavity is arranged on the training aid shell. The training aid is convenient to use, a plurality of English words can be displayed one time by providing an opening and closing plate body and an elastic rope and controlling use of the Chinese character cards through a rotating shaft, and the training aid is intuitional in form and specific and visual in content, so that English learning becomes lively and interesting, and the learning and memory of English words are facilitated.
Owner:QINGDAO AGRI UNIV
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