45 results about "Cmos voltage controlled oscillator" patented technology

As wireless communication technology evolves, various transceivers become integrated into a single system, which implements a seamless connection to search available frequency bands and to provide wireless connections regardless of their wireless standards. One of the key technologies for seamless implementation is an ultra-wideband local oscillator, which can overcome the restriction of limited tuning range in typical RF local oscillators. Many RF oscillators incorporate LC-tuned oscillators because of their good noise performance while their tuning range is limited by fixed inductance and varied capacitance. The planar inductor fabricated on the CMOS process occupies a large area as well. By replacing the planar inductor with the array of bondwires, and including switches to provide proper impedance for the circuit to generate negative impedance, the tuning range of a CMOS voltage-controlled oscillator (VCO) is extended more than 100%, which number can not be achieved in a convention VCO.

The present invention discloses an LC voltage-controlled oscillator with low tuning gain variation. The LC voltage-controlled oscillator comprises a parallel inductance-capacitance resonance circuit, two pairs of transistors which are crossly coupled and connected, a pressure controlled variable capacitor, a switch variable capacitor array and a switching capacitor array. The variation range of pressure controlled variable capacitor is adjusted through the switch variable capacitor array for counteracting the effect of oscillation frequency to tuning gain. The invention adjusts the magnitude of variable capacitor switched into the resonant circuit with a digital control signal according to the variation of oscillation frequency, and changes the regulation range of equivalent variable capacitor along with the difference of sub-band thereby counteracting the effect of oscillation frequency change to the tuning gain of voltage controlled oscillator, realizing the design of wideband voltage controlled oscillator with low tuning gain variation, and simultaneously not adding additional power consumption.

The invention provides a switched capacitor DC-DC converter. The switched capacitor DC-DC converter comprises an output sampling branch, a dead area control module for generating the dead area and outputting multiunit clock signals which has the same frequency as the input clock, a switched capacitor array module for receiving multiunit clock signals which are not overlapped and sent by the dead area control module, an error amplifier for receiving the voltage signal from the output sampling branch and the reference voltage signals, and a voltage controlled oscillator for receiving the output voltage signals of the error amplifier and for outputting the clock signals with corresponding frequency. The voltage controlled oscillator sends the clock signals to the dead control module. The frequency variation of the clock signals is in proportion to the output voltage variation of the error amplifier. The converter has low output voltage ripple and high efficiency in full load range.

A voltage-controlled oscillator (VCO) for a phase-locked loop (PLL) has improved bandwidth and performance at lower frequency. A variable current source supplies a current to an internal oscillator-power node. The current varies with the VCO input voltage. The internal oscillator-power node drives the sources of p-channel transistors in inverter stages in the ring oscillator. The variable current causes the internal oscillator-power node's voltage to vary, which varies the output frequency. An active resistor is in parallel with the ring oscillator. The active resistor has a resistor and an n-channel transistor in series between the oscillator-power node and ground. The n-channel transistor has a fixed bias voltage on its gate and is non-linear. The non-linear effective resistance of the n-channel transistor improves overall linearity of the ring oscillator. The parallel effective resistance of the active resistor lowers overall effective resistance of the ring oscillator. Oscillator bandwidth at lower frequencies improves.

A system provided for controlling an output frequency of a voltage controlled oscillator relative to a reference frequency. A method includes the steps of detecting a phase error between a divided output of the voltage controlled oscillator and the reference frequency, pumping a frequency control input of the voltage controlled oscillator with the phase error and adjusting a pumping gain based upon a magnitude of the frequency control input to the voltage controlled oscillator. The apparatus includes a phase detector adapted to detect the phase error between the divided output of the voltage controlled oscilator and the reference frequency and a charge pump adapted to pump the frequency control input of the voltage controlled oscillator with the phase error. The apparatus also includes a gain controller adapted to adjust the pumping gain based upon the magnitude of the frequency control input to the voltage controlled oscillator.

A voltage controlled oscillator of a phase locked loop circuit having digitally controlled gain compensation. The digital control circuitry provides binary logic input to the voltage controlled oscillator for a digitally controlled variable resistance circuit, a digitally controlled variable current transconductor circuit, or differential transistor pairs having mirrored circuitry for adjusting the V-I gain. The latter configuration requires the voltage controlled oscillator to incorporate a source-coupled differential pair which is driven by a low pass filter capacitor output voltage, and connected to load transistors; a current source and a current mirror for generating a tail current; individual banks of transistors to mirror the load transistor currents; a digital-to-analog converter with control lines outputted there from, the digital-to-analog converter used to increase the amount of current allowed to flow to the transconductor output, the current being digitally increased and decreased corresponding to an amount of current pulled from the current source, and mirroring the current through at least one transistor mirror circuit.

A linear fractional-N synthesizer includes phase and frequency detection module, a charge pump circuit, a loop filter, a voltage controlled oscillator, and a fractional-N divider. The phase and frequency detection module is operably coupled to produce a charge up signal, a charge down signal, or an off signal based on a phase difference and/or a frequency difference between a reference oscillation and a feedback oscillation. The charge pump circuit is operably coupled to produce a positive current when the charge up signal is received, a negative current when the charge down signal is received, and a non-zero offset current when the off signal is received. The charge pump includes a resistor and a control module. The resistor provides the non-zero offset current and the control module maintains the non-zero offset current at a substantially constant value. The loop filter is operably coupled to produce a control voltage based on at least some of: the positive current, the negative current, and the non-zero offset current. The voltage controlled oscillator produces an output oscillation based on the control voltage. The fractional-N divider module operably coupled to divided the output oscillation by a fractional N value to produce the feedback oscillation.

A method and apparatus for varactor bank switching for a voltage controlled oscillator is disclosed. Varactor bank switching involves generating a negative bias voltage signal as a control signal for a varactor bank switch in an off-state, the varactor bank switch comprising a pass-gate circuit including switching transistors. Generating the negative bias voltage signal includes employing an active rectifier circuit running at the speed of an oscillation signal, the negative bias voltage signal maintaining the gate-source voltage of the pass-gate circuit below a threshold voltage to prevent said switching transistors from becoming conductive in an off-state.

A local signal generation circuit in accordance with one aspect of the present invention includes a phase comparator that detects a phase difference between a reference signal and a feedback signal and outputs a error signal, a charge-pump circuit that receives the error signal and generates a step-up voltage, a loop filter that generates a tuning voltage by changing the shape of the step-up voltage, a voltage control oscillator that generates a first output signal having a predefined frequency based on the tuning voltage, and a prescaler that outputs a second output signal generated by dividing the frequency of the first output signal to a predefined frequency and also outputs a frequency-division signal generated by dividing the frequency of the first output signal to the predefined frequency to a frequency divider that generates the feedback signal.

A phase locked loop (PLL) circuit includes a voltage controlled oscillator (VCO) having a parallel resonant circuit including a first capacitance implemented by a reverse-biased diode and a second capacitance implemented by MOS capacitors. Upon lock-in of the oscillation frequency with respect to the reference frequency, whether the oscillation frequency has a deviation is examined based on the tune voltage controlling the first variable capacitance. If a deviation is observed due to a temperature fluctuation etc., the control voltage for the second variable capacitance is corrected for compensating the deviation.

The invention provides a voltage controlled oscillator circuit, which consists of at least three stages of total difference unit circuits which are cascaded mutually and are completely same. The circuit has the advantages that: 1, the circuit is a CMOS voltage controlled oscillator circuit which has simple structure, high reliability, wide frequency regulating range, and can operate normally under extremely low power supply voltage; 2, the circuit can select a cascade mode of three-stage and above three-stage total difference units which are completely same; 3, source electrodes of positive feedback active load are directly earthed for improving one pass gain of the total difference units, thereby ensuring that the oscillator circuit can normally start oscillation under any condition; 4, a voltage clamping circuit plays a role of stabilizing amplitude of an output signal of the oscillator; and 5, when control voltage controls current in a tail current source of the difference unit to generate variation through certain V-I converting circuit, the oscillator circuit can generate output waveforms with different frequencies along with the magnitude of the tail current, as long as the current in the tail current source is invariable, the frequency of the output waveform of the oscillator circuit can be invariable.

In a PLL frequency synthesizer, a linearization circuit (6) is provided which receives an oscillation frequency control signal (VT) from a loop filter (LF). The linearization circuit (6) outputs, in accordance with the potential level of the oscillation frequency control signal (VT), a charge pump current control signal (CPCONT) that exhibits the higher value, the higher the potential level. The charge pump (CP) receives the charge pump current control signal (CPCONT) to cause a current in accordance with the value of the received charge pump current control signal (CPCONT) to flow in or flow out. Thus, a simple circuit arrangement can be used to adjust and maintain constant the loop gain characteristic of the PLL frequency synthesizer. Accordingly, even when a variable capacitance element included in the a voltage controlled oscillator has a nonlinear characteristic for the potential of the input oscillation frequency control signal, the loop gain of the PLL frequency synthesizer having this voltage controlled oscillator can be adjusted and maintained constant.

The frequency of a first voltage controlled oscillator is stabilized in a first PLL circuit part into which a reference frequency signal is inputted. In addition, a second PLL circuit part is formed by inputting a control voltage which is the same as the frequency control voltage of the first voltage controlled oscillator into a second voltage controlled oscillator having the same configuration as the first voltage controlled oscillator. The first PLL circuit part is provided with first and second variable frequency dividers which respectively divide the reference frequency signal and the output of the first voltage controlled oscillator. In response to an input signal into the second PLL circuit part, the free-running frequencies of the second and first voltage controlled oscillators are switched, and at the same time, the division ratio of first and second variable frequency dividers are switched.