30results about How to "Adjust capacitance" patented technology

A pixel structure including an active device, a common line pattern, a protective layer, a pixel electrode, and a patterned semiconductor layer is provided. The active device is disposed on a substrate. In addition, the common line pattern is disposed on the substrate and covered with an insulation layer. The protective layer covers the active device and a part of the insulation layer. The protective layer has a contact window exposing the active device. The pixel electrode is disposed on the protective layer and electrically connected to the active device through the contact window. The patterned semiconductor layer is disposed on the insulation layer above the common line pattern. The patterned semiconductor layer is located between the common line pattern and the pixel electrode.

A semiconductor device includes a semiconductor chip, a dielectric substrate, and bonding wires. The dielectric substrate includes wiring patterns formed on a surface and a ground metal layer formed on a back side. The semiconductor chip includes an active element and a drain pad that is connected to an output end of the active element. Wiring pattern is formed at a position closer to the drain pad than wiring pattern, wiring pattern and the ground metal layer constitute a first capacitative element, and wiring pattern and the ground metal layer constitute a second capacitative element. The drain pad is connected to wiring pattern through bonding wire, and connected to wiring pattern through bonding wire. Bonding wire and the first capacitative element constitute a high-pass matching circuit.

The present disclosure provides an adjustable capacitor comprising a ferroelectric dielectric layer, a first electrode and a second electrode disposed on opposite sides of the ferroelectric dielectric layer. The adjustable capacitor further comprises a first control electrode and a second control electrode insulated from the first electrode and the second electrode. The first control electrode and the second control electrode are configured to provide an electric field to the ferroelectric dielectric layer, to adjust a dielectric constant of the ferroelectric dielectric layer by controlling an electric field strength, thereby adjusting the capacitance between the first and the second electrodes. The present disclosure also provides an impedance matching device and a semiconductor processing apparatus. The adjustable capacitor, the impedance matching device and the semiconductor processing apparatus can adjust the capacitance of the adjustable capacitor in milliseconds, thereby accelerating the matching speed, shortening the matching time, and improving the processed result.

The invention provides a circuit board structure and a manufacturing method thereof. The circuit board structure includes an insulating layer, a first circuit layer and a second circuit layer on opposite sides of the insulating layer, and the insulating layer is penetrated to electrically connect the first circuit layer and the second circuit layer. Conductive vias, capacitor dielectric layers, dielectric layers and redistributed circuit layers of the circuit layer. The first wiring layer includes a first capacitor electrode. The capacitive dielectric layer is located on the first capacitive electrode. The dielectric layer covers the first circuit layer and the capacitor dielectric layer. The redistributed circuit layer includes a redistributed circuit on the dielectric layer, a first conductive blind hole located in the dielectric layer and connected to the first circuit layer, and a second capacitor electrode located in the dielectric layer. Two ends of the second capacitor electrode are respectively in contact with the capacitor dielectric layer and the redistribution line. The second capacitor electrode, the capacitor dielectric layer and the first capacitor electrode constitute a capacitor.

The invention belongs to the cross-technical field of filter capacitors, micro-nano manufacturing technology and electronic circuits, and discloses a preparation method and application of a chip-type micro-filter capacitor, which adopts a patterned 3D silicon-based frame (100) to conduct current collectors ( 101) and the coating of active material (102), make the electrode of capacitor, fix it on the lower part (103a) of the packaging case, coat the electrolyte (104); finally package the upper part of the case (103b) and reserve a conductive connection point, The conductive pin (105) is embedded in the shell to realize the chip design conductive pin of the capacitor. The present invention designs the overall flow process of the chip-type micro-filter capacitor, and realizes the customized manufacturing of the chip electrode through the semiconductor process; adopts a simple packaging structure, which is convenient for sealing; and manufactures a pair of embedded conductive pins with adjustable dimensions. The circuit board is electrically connected by spot welding, which ensures connection reliability and miniaturized integration. Finally, it is actually applied to the patch circuit board to realize the filtering function.

The present invention relates to a vacuum capacitor (1, 30) comprising an enclosure (9) to contain a vacuum dielectric medium, a first electrode (12) and a second electrode (13) separated by said vacuum dielectric medium, the enclosure (9) comprising a first conductive collar (2) in electrical contact with the first electrode (12) and a second conductive collar (3) in electrical contact with the second electrode (13), the first conductive collar (2) and the second conductive collar (3) being separated by an insulating element (4) of the enclosure (9), wherein the enclosure (9) exhibits at least one protruding edge (6), said protruding edge (6) being in electrical contact with the closest of the first conductive collar (2) or the second conductive collar (3), wherein the vacuum capacitor (1, 30) comprises at least one protection means (7, 37) covering on the outside of the vacuum enclosure the protruding edge (6), wherein the protection means (7, 37) is made at least partially of an elastomer, wherein at least the outer surface (7b, 37b) of the protection means (7, 37) is electrically conductive and is at the same electrical potential as the closest conductive collar to the protruding edge (6), and wherein the outer surface (7b, 37b) of the protection means (7, 37) has a radius of curvature greater than the radius of curvature of the protruding edge (6).

A position indicator includes a resonance circuit housed in a casing and having an inductance element and a capacitor variable in capacitance, such that the resonance circuit resonates at a predetermined frequency. The position indicator is electromagnetically coupled to a position detecting device. The capacitor includes a dielectric, an electrode disposed on one side of the dielectric, and a trimming electrode disposed on another side of the dielectric such that at least one part of a region of the trimming electrode is opposed to the electrode with the dielectric interposed in between, to form the capacitance of the capacitor. The capacitor is housed in the casing such that the at least one part can be exposed from the casing. The area of the at least one part exposed from the casing to the outside is changed so as to correspond to a resonance frequency desired for the resonance circuit.