Provided is a
semiconductor memory device including an
oxide semiconductor insulated gate FET and having a capability to implement advanced performance without being affected by a variation in
threshold voltage. A
memory cell MC includes a memory node Nm formed at a connection point of a gate of a first
transistor element T1, a source of a second
transistor element T2, and one end of a capacitive element Cm, and a control node Nc formed at a connection point of a drain of the first
transistor element T1 and a drain of the second transistor element T2. Each
memory cell MC arranged in the same column includes the control node Nc connected to a shared first
control line CL extending in a column direction, the first transistor element T1 having a source connected to a shared
data signal line DL extending in the column direction, the second transistor element T2 having a gate connected to an individual first selection line WL, and the capacitive element Cm having the other end connected to an individual second selection line GL, and a switching element SE having one end connected to the first
control line CL, and the other end connected to a
voltage supply line VL is provided with respect to each first
control line CL.