249results about "Amplifiers with min 3 electrodes or 2 PN junctions" patented technology

According to an embodiment, a method includes amplifying a signal provided by a capacitive signal source to form an amplified signal, detecting a peak voltage of the amplified signal, and adjusting a controllable impedance coupled to an output of the capacitive signal source in response to detecting the peak voltage. The controllable impedance is adjusted to a value inversely proportional to the detected peak voltage.

A method and apparatus provides techniques for electrically isolating switching devices in a stacked RF power amplifier, which prevents the switching devices from being subjected to high breakdown voltages. The isolation provided allows the power amplifier to be implemented on an integrated circuit.

A multi-stage amplifier circuit arranged to take advantage of the desirable characteristics of non-field-plate and field plate transistors when amplifying a signal. One embodiment of a multi-stage amplifier according to the present invention comprises a non-field-plate transistor and a field-plate transistor. The field-plate transistor has at least one field plate arranged to reduce the electric field strength within the field plate transistor during operation. The non-field plate transistor is connected to the field plate transistor, with the non-field-plate providing current gain and the field plate transistor providing voltage gain. In one embodiment the non-field-plate and field plate transistors are coupled together in a cascode arrangement.

This disclosure describes systems, methods, and apparatuses for impedance-matching radio frequency power transmitted from a radio frequency generator to a plasma load in a semiconductor processing chamber. Impedance-matching can be performed via a match network having a variable-reactance circuit. The variable-reactance circuit can comprise one or more reactive elements all connected to a first terminal and selectively shorted to a second terminal via a switch. The switch can comprise a bipolar junction transistor (BJT) or insulated gate bipolar transistor (IGBT) controlled via bias circuitry. In an on-state, the BJT base-emitter junction is forward biased, and AC is conducted between a collector terminal and a base terminal. Thus, AC passes through the BJT primarily from collector to base rather than from collector to emitter. Furthermore, the classic match network topology used with vacuum variable capacitors can be modified such that voltages do not overload the BJT's in the modified topology.

Provided is a circuit to perform single-ended to differential conversion while providing common-mode voltage control. The circuit includes a converter to convert a single-ended signal to a differential signal and a stabilizing circuit adapted to receive the differential signal. The stabilizing circuit includes a sensor configured to sense a common-mode voltage level of the differential signal and a comparator having an output port coupled to the converter. The comparator is configured to compare the differential signal common-mode voltage level with a reference signal common-mode voltage level and produce an adjusting signal based upon the comparison. The adjusting signal is applied to the converter via the output port and is operative to adjust a subsequent common-mode voltage level of the differential signal.

A method and apparatus provides techniques for electrically isolating switching devices in a stacked RF power amplifier, which prevents the switching devices from being subjected to high breakdown voltages. The isolation provided allows the power amplifier to be implemented on an integrated circuit.

A reduction is achieved in the primary-side input impedance of a transformer (voltage transformer) as an output matching circuit without involving a reduction in Q-factor. An RF power amplifier includes transistors, and a transformer as the output matching circuit. The transformer has a primary coil and a secondary coil which are magnetically coupled to each other. To the input terminals of the transistors, respective input signals are supplied. The primary coil is coupled to each of the output terminals of the transistors. From the secondary coil, an output signal is generated. The primary coil includes a first coil and a second coil which are coupled in parallel between the respective output terminals of the transistors, and each magnetically coupled to the secondary coil. By the parallel coupling of the first and second coils of the primary coil, the input impedance of the primary coil is reduced.

The invention is directed to a system for electromagnetic communications that includes a semiconductor die; at least one amplifier on the die to amplify an input signal and generate an output signal; and an active bias control component on the die for adjusting biasing of the amplifier so that the amplifier is operable in a plurality of frequency bands. In one embodiment, a PCS band and W-CDMA power amplifier may be integrated on the same power amplifier die, and different output power requirements may be addressed by the use of an Si DC-DC converter. Such a converter may provide efficiency enhancements to the overall system through the use of dynamic bias control under active power control situations from the network. In addition, the converter may be used in a voltage up-converter state that allows a W-CDMA optimized power amplifier to operate at PCS frequencies and output power levels.

Synthetic circuit elements and amplifier applications for synthetic circuit elements are provided. The synthetic circuit elements disclosed herein may be configured to compensate for some or all of the parasitic capacitance normally associated with circuit elements disposed on a substrate providing a selectable impedance characteristic. Amplifier circuit constructed using such synthetic circuit elements exhibit improved performance characteristics such as improved recovery time, frequency response, and time domain response.

A power amplifier module for amplifying radio frequency signals includes first, second, third and fourth corner ground pads positioned at each corner of the power amplifier module; a radio frequency input pad positioned between the first and second corner ground pads; a radio frequency output pad positioned between the third and fourth corner ground pads; and a power amplifier circuit centrally positioned on the power amplifier module, the power amplifier having an input coupled to the radio frequency input pad and an output coupled to the radio frequency output pad.

Embodiments of the invention are concerned with configurable RFICs. In an exemplary embodiment there is provided a configurable radio-frequency integrated circuit (RFIC) including one or more configurable low noise amplifier circuits, each of said one or more configurable low noise amplifier circuits being configurable between:an internal input impedance matching topology in which the respective low noise amplifier circuit includes one or more internal input impedance matching components adapted to match the input impedance of the respective low noise amplifier to a given input, said one or more internal input impedance matching components being located internally to the respective low noise amplifier circuit; anda topology different from said internal input impedance matching topology.

A wireless communication system includes: a filter; and a semiconductor chip including a signal processing integrated circuit having an amplifier, wherein a main surface of the semiconductor chip is provided with a plurality of electrode terminals along an edge portion thereof; wherein the amplifier has a transistor including a control electrode, a first electrode through which a signal is outputted, and a second electrode to which a voltage is applied; wherein the control electrode, the first electrode and the second electrode of the transistor are connected to the electrode terminals, respectively; and wherein none of wirings are arranged between the electrode terminals and placements of the control electrode, the first electrode and the second electrode, making space between the electrodes and the electrode terminals narrow.

Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.

A novel RF power amplifier integrated circuit (PA IC), unit cell, and method for amplifying RF signals are disclosed. One embodiment of a PA IC includes at least two linear arrays comprising transistor device units, and at least one linear array comprising capacitors. The transistor device units include source nodes that are jointly coupled to a source bus, and selected gate nodes that are jointly coupled to a gate bus. First electrodes of the capacitors are also jointly coupled to the source bus, and second electrodes of the capacitors are jointly coupled to the gate bus. Each linear array comprising capacitors is disposed between at least two linear arrays comprising transistor device units. In one embodiment, the PA IC includes unit cells. In some embodiments, each unit cell comprises two transistor device units and one or more capacitors. The capacitors are disposed between the transistor device units. The unit cells are disposed in linear arrays so that the transistor device units are disposed in linear arrays and the capacitors are disposed in linear arrays.

An amplifier output impedance matching configuration including a first impedance transformer and one or more second impedance transformers. The first impedance transformer receives input signals from a power amplifier and generates output signals to a load. The one or more second impedance transformers are connected between the first impedance transformer and the load through which the output signals are passed.

Optical receiver circuit having a first, illuminable reception device for converting an optical signal into an analog electrical signal; a first preamplifier for amplifying the output signal of the first reception device; a postamplifier having a first input and a second input, the first input being supplied with the signal of the first reception device (said signal having been amplified in the first preamplifier) and the second input being supplied with a reference signal; an offset compensation circuit, which regulates the difference between the mean value of the electrical signal at the first input of the postamplifier and the reference signal at the second input of the postamplifier to a constant value; and having a signal detection device, which detects a control signal of the offset compensation circuit and carries out signal detection in a manner dependent on this signal. The invention provides signal detection in an optical receiver circuit, which manages with few additional components.

Aspects of the invention are related to a power semiconductor module applied to a multi-level converter circuit with three or more levels of voltage waveform. Aspects of the invention can include a first IGBT to which a diode is reverse parallel connected and a second IGBT having reverse blocking voltage whose emitter is connected to the emitter of the first IGBT are housed in one package, and each of the collector of the first IGBT, the collector of the second IGBT, and the connection points of the emitter of the first IGBT and the emitter of the second IGBT, is an external terminal.

A small-sized on-chip complementary metal-oxide semiconductor (CMOS) Power Amplifier having improved efficiency is provided herein. The on-chip CMOS power amplifier is capable of improving efficiency and maximizing output thereof by enhancing a K factor, which may cause a problem in a power amplifier having a distributed active transformer structure. The on-chip CMOS power amplifier having an improved efficiency and being fabricated in a small size, the on-chip CMOS power amplifier includes a primary winding located at a first layer, secondary windings located at a second layer, which is an upper part of the first layer, the secondary windings being located corresponding to a position of the primary winding, and a cross section for coupling the second windings with each other.

The present invention provides a single chain power amplifier for a multi-mode and / or multi band wireless communication. The power amplifier comprise switchable input, inter-stage and output matching networks as well as active periphery adjustable driver stage power device and power stage power device. Switches and bias are configured for each frequency band and / or wireless communication standard. A driver stage power device, switches, control and bias circuitry, input matching, inter-stage matching and a part of output matching is fabricated on CMOS Silicon On Insulator process (SOI), while a power stage power device maybe fabricated by Gallium Arsenide (GaAs) processing.

In a high frequency power amplifier module of a multi-stage structure in which a plurality of heterojunction bipolar transistors (npn-type HBTs) are cascade-connected, a protection circuit in which a plurality of pn junction diodes are connected in series is connected between the collector and emitter of each HBT. The p-side is connected to the collector side, and the n-side is connected to the emitter side. A protection circuit in which pn junction diodes of the number equal to or smaller than that of the pn junction diodes are connected in series is connected between the base and the emitter. The p-side is connected to the base side, and the n-side is connected to the emitter side. With the configuration, in the case where an overvoltage is applied across the collector and emitter due to a fluctuation in load on the antenna side, the collector terminal is clamped by an ON-state voltage of the protection circuits, so that the HBT can be prevented from being destroyed. Since the similar protection circuit is assembled between the base and emitter, even when the operator touches the module at the time of manufacturing the high frequency power amplifier module, the HBT can be prevented from being destroyed by the clamping effect of the protection circuit between the base and emitter and the protection circuit between the collector and emitter. Thus, an improved manufacturing yield of the high frequency power amplifier module and a wireless communication apparatus can be achieved, and destruction caused by fluctuation in load impedance of the wireless communication apparatus can be prevented.

A small, high performance high frequency power amplifier enables easily adjusting and switching the impedance. The high frequency power amplifier module includes a first semiconductor chip including one or a plurality of high frequency amplification devices, and a second semiconductor chip including one or more high frequency matching circuit devices and one or more switching devices. The second semiconductor chip includes the matching circuit for a high frequency amplifier device. The second semiconductor chip also includes a circuit composed of a capacitance and a switching device connected in series or parallel to the capacitance. The switching device switches on or off so that the capacitance is connected or is not connected as a part of the matching circuit.

Disclosed are devices and methods for improving power added efficiency and linearity of radio-frequency power amplifiers implemented in flip-chip configurations. In some embodiments, a harmonic termination circuit can be provided so as to be separate from an output matching network configured to provide impedance matching at a fundamental frequency. The harmonic termination circuit can be configured to terminate at a phase corresponding to a harmonic frequency of the power amplifier output. Such a configuration of separate fundamental matching network and harmonic termination circuit allows each to be tuned separately to thereby improve performance parameters such as power added efficiency and linearity.

A small-sized on-chip complementary metal-oxide semiconductor (CMOS) Power Amplifier having improved efficiency is provided herein. The on-chip CMOS power amplifier is capable of improving efficiency and maximizing output thereof by enhancing a K factor, which may cause a problem in a power amplifier having a distributed active transformer structure. The on-chip CMOS power amplifier having an improved efficiency and being fabricated in a small size, the on-chip CMOS power amplifier includes a primary winding located at a first layer, secondary windings located at a second layer, which is an upper part of the first layer, the secondary windings being located corresponding to a position of the primary winding, and a cross section for coupling the second windings with each other.

A low-noise, fast-settling bias circuit includes a first and a second low pass filter, such as RC filters. The second filter initially shorts out a resistor of the first filter with a switch (set to low impedance) in parallel. Accordingly, a capacitor of the first filter quickly charges up to the same voltage as the input bias voltage. As the second filter charges up, the switch slowly shuts off (high impedance). By this time, since the capacitor of the first filter has charged to the same voltage as the bias voltage, a large RC formed by the resistor of the first filter and the capacitor of the first filter is available to provide filtering for the desired bias current.

Electronic circuits and methods are provided for various applications including signal amplification. An exemplary electronic circuit comprises a MOSFET and a dual-gate JFET in a cascode configuration. The dual-gate JFET includes top and bottom gates disposed above and below the channel. The top gate of the JFET is controlled by a signal that is dependent upon the signal controlling the gate of the MOSFET. The control of the bottom gate of the JFET can be dependent or independent of the control of the top gate. The MOSFET and JFET can be implemented as separate components on the same substrate with different dimensions such as gate widths.

A path configuration for a power switch and driver can introduce independent parasitic inductance coupled to the power switch to slow a switching speed of the switch and reduce voltage spikes on the switch during switching events. The path for low side supply of the drive to the negative DC voltage reference is separate from the path of the power switch to the reference. The resulting reduction in voltage spikes due to the slowed switching time maintains performance in an audio amplifier without modifying a switch command signal to compensate for voltage spikes. The path configuration avoids reliance on specifying higher rated components that increase application costs.

In one embodiment, the present invention includes an amplifier having a transistor stage coupled between a supply voltage and a bias current. The transistor stage has an input to receive a radio frequency (RF) input signal obtained from an antenna. The amplifier has an input impedance that is unmatched to a source impedance of the antenna. In some embodiments, this unmatched input impedance may be substantially greater than the source impedance, and may further be controlled based on a strength of the RF input signal.

A MMIC amplifier stage and a discrete transistor amplifier stage are housed in a single package. In one aspect, a multi-stage RF amplifier includes a package with an RF input lead and an RF output lead. The signal path from the RF input lead to the RF output lead includes one or more MMIC amplifier stages followed by one or more discrete transistor amplifier stages. Each MMIC amplifier stage includes a MMIC with at least one amplifier, and each discrete transistor amplifier stage includes at least one discrete transistor amplifier. All of the MMIC amplifier stages and discrete transistor amplifier stages are housed in the same package.