38 results about "Left half plane" patented technology

An apparatus for estimating a facial pose. The apparatus includes a pre-processing module that provides feature points of a subject's face of a received image, and a pose-estimation module that computes sizes of a left half plane and a right half plane of the face from the provided feature points, and a lateral rotation angle of the face from the computed sizes.

The invention discloses a common-mode feedback circuit frequency compensation method of a dual-stage amplifier, which belongs to the analog integrated circuit design field. One common-mode feedback circuit is adopted in the dual-stage amplifier to reduce the area and the power consumption of the feedback circuit; the dual-stage amplifier adopts a fully-differential input/output structure; a differential output terminal is used for sampling the common-mode output level; a first-stage amplifying circuit thereof comprises a controllable biasing circuit; a common-mode feedback control signal controls the first-stage common-mode output level and the second-stage common-mode output level of the amplifier at the same time through the controllable biasing circuit; a feedback amplifier is realized by adopting a dual-stage operational amplifier with miller compensation. The left half plane zero point generated by the feedback amplifier in a loop circuit counteracts a certain left half plane pole in a prime amplifier, thereby forming a stable compensation loop circuit. The common-mode feedback circuit frequency compensation method has the advantages of less feedback circuit elements, lower feedback circuit power consumption, high low-frequency loop gain and better compensation phase margin.

The invention discloses an operational amplifier. The operational amplifier comprises a first-stage amplification circuit and a second-stage amplification circuit, wherein the first-stage amplification circuit is a single-end output differential amplification circuit, the inverted phase output end of the single-end output differential amplification circuit serves as the output end of the first-stage amplification circuit, and a first-stage amplification signal is output; the input end of the second-stage amplification circuit is connected with the output end of the first-stage amplification signal, and a second-stage amplification signal is output; a first capacitor is connected between the input end and the output end of the second-stage amplification circuit; the second-stage amplification circuit comprises a first MOS (Metal Oxide Semiconductor) transistor; the first MOS transistor is connected with the output end of the second-stage amplification circuit and provides a current source load for the second-stage amplification circuit; the inverted phase input end of the single-end output differential amplification circuit is connected to a gate of the first MOS transistor through a second capacitor to form a feed-forward path; the trans-conductance of the first MOS transistor is set to be greater than that of the first-stage amplification circuit, so that a left half plane zero point is formed by the operational amplifier. The stability of the operational amplifier can be improved.

The invention relates to a turning network transconductor, namely a capacitance compensating circuit which comprises a main signal transconductor, a feedforward compensating transconductor, a compensating capacitor and a loading capacitor, wherein the main signal transconductor comprises N+1 main signal transconductance units which are in step linkage to form a main signal path, the feedforward compensating conductance comprises N feedforward compensating conductance units which are used for forming a left half-plane zero point and improving the phase margin, the compensating capacitor comprises N capacitors used for improving the stability of a high-conductance amplifier because the Miller effect enables main poles are separated from non-main poles, and the loading capacitor comprises a capacitor forming the pole of a conductance amplifier with a loading resistor. An RNGCC circuit provided by the invention effectively improves the phase margin, has simple structure and is suitable for the necessary low power supply voltage of the future CMOS technology, and the applying prospect is wide.

The invention discloses an operational amplifier, which comprises a first-stage amplifier circuit and a second-stage amplifier circuit, wherein the first-stage amplifier circuit is a single-ended output differential amplifier circuit; a grid of a first MOS (Metal Oxide Semiconductor) transistor and a grid of a second MOS transistor are respectively taken as a non-inverting input terminal and an inverting input terminal of the single-ended output differential amplifier circuit; a drain of an eleventh PMOS (P-channel Metal Oxide Semiconductor) tube is taken as an inverting output terminal and outputs a first-stage amplifying signal; an input end of the second-stage amplifier circuit is connected to the first-stage amplifying signal; and a seventh MOS transistor is connected to an output end of the second-stage amplifier circuit and provides current source load for the second-stage amplifier circuit. A second capacitor and the seventh MOS transistor form a feedforward path between the inverting input terminal of the single-ended output differential amplifier circuit and the output end of the second-stage amplifier circuit; the transconductance of the seventh transistor is arranged to be greater than the transconductance of the first-stage amplifier circuit, so that the operational amplifier forms left half plane zero to offset a pole in order to realize an effect of improving the stability of the circuit.

In a preferred embodiment, a voltage inverter comprises a voltage converter circuit and a controller. The voltage inverter produces a time-varying output voltage from an input voltage, which can be a DC input voltage or an AC input voltage. The controller provides a control signal at a duty ratio determined dynamically by a set of signals. The set of signals include the time-varying output voltage, a predetermined output voltage, a gain factor and an inductor current in the voltage converter circuit. The predetermined output voltage can have an AC waveform or an arbitrary time-varying waveform. The voltage inverter operates to match the time-varying output voltage to the predetermined output voltage. Input-output linearization is used to design a buck inverter, and input-output linearization with leading edge modulation is used to design boost and buck-boost inverters under conditions where left half plane zero effects are present.

The invention relates to the stability analysis technology in the DC micro-grid technologies, and aims to provide a stability determination method for a DC micro-grid in the master-slave control mode. The method comprises the following steps: using the unit connection method to carry on the Thevenin/Norton equivalent to the power modules of each power supply and each constant power load so as to obtain the corresponding impedance/admittance, and obtaining the impedance matrix of the main power supply, the admittance matrixes of the slave power source and the constant power load; according to the known resistive load size of each node, obtaining the resistive load admittance matrix, and obtaining the system node admittance matrix according to the inter-node cable parameter; placing each matrix into the stability criterion and calculating its pole; if all the poles are on the left half plane, determining that the system is stable; and if there is a pole on the right half plane, determining the system is unstable. The method is compatible with the inter-node impedance of the system, and has no specific requirement for the system structure, and has a wide application range. The calculation is simplified in the system-level stability analysis and the stability of the complex DC micro-grid can be effectively analyzed.

The invention provides a frequency compensation circuit for an operational amplifier. The frequency compensation circuit comprises a gain circuit, an output circuit and a tail current source bootstrap circuit of the gain circuit, wherein a grounding end of the gain circuit is connected with a first end and a second end of the tail current source bootstrap circuit; an output end of the gain circuit is connected with a first input end of the output circuit and an input end of the tail current source bootstrap circuit respectively; an output end of the tail current source bootstrap circuit is connected a bias voltage, and connected with a second input end of the output circuit through a first resistor; and the second input end of the output circuit is connected with the output end of the gain circuit through a first capacitor. Based on an RC network consisting of the first resistor and the first capacitor, the operational amplifier generates a left-half plane null point z, and the left-half plane null point z and a first non-main pole of the operational amplifier can be counteracted by adjustment of the magnitude of the RC, so that frequency compensation of the operational amplifier is realized. Meanwhile, the unit gain bandwidth of the operational amplifier can be increased remarkably.

In a preferred embodiment, a voltage converter comprises a voltage converter circuit, an output adjuster and a controller. The controller provides a control signal at a duty ratio determined dynamically by a set of input signals. The dynamic output adjuster determines the set of input signals by adjusting the ac component of an output voltage based on a gain Q. The dynamic output adjuster alleviates dependence on the value of R_c under leading edge modulation in either analog or digital converter systems. In addition to delivering the desired left half plane zero effects, dynamic output adjustment reduces the value of the output ripple. As a result, modern control methods such as input-output linearization can be used to design both boost and buck-boost PWM converters if only left half plane zero effects are present.

The invention belongs to the technical fields of power grid performance testing devices and electrical fault detection devices, and discloses a power grid voltage frequency and phase angle detection method. The method comprises the steps that a single-phase power grid voltage signal is acquired, an integrator and a state observer are constructed, a power grid voltage signal and an orthogonal signal thereof are obtained and substituted into a phase-locked loop formula by serving as variables, and then frequency and phase angle information of a power grid is obtained. According to the method, key information such as the amplitude, the frequency and the phase angle of the power grid is measured by using a PLL; the dynamic response speed is high, and the excellent steady-state precision is achieved under the conditions of power grid frequency changes and harmonic interference; a QSG is designed from the angle of the observer, pole configuration is more flexible, poles can be configured ona left half plane arbitrarily, and the range that parameters can be adjusted is wider; and the dynamic response speed and the harmonic suppression capacity are high. When the method is used for measuring the power grid voltage, the better dynamic performance and the better harmonic suppression performance are achieved, the parameter configuration range is wider, and arbitrary configuration can beachieved on the left half plane.

The invention relates to a three-stage transconductance amplifier design. The three-stage transconductance amplifier is characterized in that NMOS (N-channel Metal Oxide Semiconductor) tubes M3/M4/M5/M6, PMOS (P-channel Metal Oxide Semiconductor) tubes M1/M2/M7/M8 and a tail current source Iss form a folding input structure and a first stage; NMOS tubes M9/M10/M11/M12 and PMOS tubes M13/M14 form a second stage; an NMOS tube M15 and a PMOS tube M16 form a third stage; NMOS tubes M17/M18, PMOS tubes M19/M20 and a capacitor Cc form a compensation structure; the input end of the compensation structure is connected to the output end of the second stage of the transconductance amplifier; and the output end of the compensation structure is connected to the output end of the transconductance amplifier. A power supply of the transconductance amplifier is vdd1, a power supply of the compensation structure is vdd2 and a capacitor CL represents a load capacitor of the transconductance amplifier. According to the three-stage transconductance amplifier, a left half plane zero is introduced into a product of a gain A of a gain stage and the capacitor Cc, so that a dominant pole of a transmission function of the three-stage transconductance amplifier is not reduced, and the transconductance amplifier is guaranteed to have relatively large -3dB bandwidth and unity-gain bandwidth.

The invention relates to the technical field of nuclear power plant steam generators and particularly disk a cuboid sodium-sodium-water integrated steam generator. A barrel in the steam generator is of a cuboid shell structure. The upper end of the barrel is provided with an upper tube plate. A plurality of sodium-water heat transfer tubes are arranged in the barrel. The two ends of the sodium-water heat transfer tubes are arranged on a left half plane and a right half plane of the upper tube plate correspondingly. The upper end of the barrel is provided with an upper sealing head. The upper sealing head and the upper tube plate are divided into two independent spaces, namely, a steam chamber and a water supply chamber, through a vertical partition board, and the steam chamber and the water supply chamber communicate with two ports of each sodium-water heat transfer tube. The sodium-water heat transfer tubes are arranged in the barrel. The outer sidewall of the barrel is provided withan encircling plate. One ports of the sodium-water heat transfer tubes on the sidewall of the barrel are enclosed to form primary sodium inlets. The encircling plate encloses the other ports of the sodium-water heat transfer tubes to form primary sodium outlets. The steam generator provided by the invention improves the heat transfer efficiency. The number of sodium circulation processes is reduced to one. The resistance in the technological process is obviously reduced.

In the vehicle surrounding viewing system 1A, the light shielding member 27, that is coated on the areas other than the effective area of the surface of the prism 4 provided in the case 3, can transmit only the ray of light 18L, that enters into the transmit window 2L of the case 3, then passes through the prism side surface 8L, and then internally reflects at the prism side surface 8R, and subsequently is focused by the focusing lens 9 to be guided to the left half plane 10L of the image pick-up plane of the image pick-up element 10, and also the ray of light 18R, that enters into the transmit window 2R of the case 3, then passes through the prism side surface 8R, and then internally reflects at the prism side surface 8L, and subsequently is focused by the focusing lens 9 to be guided to the right half plane 10R of the image pick-up plane of the image pick-up element 10.

The invention discloses a coupling delay synchronization network system and a design method thereof, wherein the network disclosed by the invention is of a dissipation coupling structure; the infinite synchronization region (minus infinity, alpha 1) of the network covers a minus real axis; and a main stabilization function curve in a left half plane is monotonically decreased, thereby enabling the synchronization speed of the network to be slowed along with the increasing of the coupling intensity. The invention also provides the design method of the coupling delay synchronization network system with the nodes which are two-dimensional and three-dimensional power systems. In the method, the main stable stabilization function curve of the network is ensured to be monotonically decreased in the left half plane under the condition that the synchronization state is a balance point by virtue of computing the coupling matrix in the rank 1, thereby becoming a coupling delay synchronization network. The network disclosed by the invention has the advantages that the synchronization speed is unidirectionally changed along with the coupling intensity, thereby facilitating the regulation and control on the synchronization speed; the network design method disclosed by the invention has the advantages of simple computation, small parameters to be determined, less transmission signals needed by the network, and low operation energy consumption.

The invention discloses a high-bandwidth high-gain trans-impedance amplifier applied to a large input capacitor, and belongs to the field of analog signal processing in laser three-dimensional imaging. The invention can adopt to application conditions of a large input capacitor, and can be especially applied to a large photosensitive surface avalanche diode array read-out circuit. The transimpedance amplifier comprises a slow path and a fast path, the slow path comprises two stages of amplifiers, the first stage of amplifier is a cascode structure formed by a second NMOS transistor and a firstNMOS transistor, the second stage of amplifier is a cascode amplifier formed by a sixth NMOS transistor MN6, and the slow path provides the main gain of the system; The eighth NMOS tube is a common-source amplifier, a fast channel is formed, a feedforward path is provided for the system, and the stability of the system is improved; The fast path and the slow path are connected in parallel in thesystem to generate a left half-plane zero point to replace a compensation capacitor in a traditional transimpedance amplifier, so that the Q value of the system is reduced, the stability of the transimpedance amplifier is realized, and the problem that the bandwidth and the gain of the traditional transimpedance amplifier are limited by the input capacitance of an avalanche diode is solved.