Down-link communication data DND from a main
control circuit unit 120A to a combination
control circuit unit 130A are divided into first and second down-
link data, and high-speed communication is performed using a down-link
clock signal CLD and a transmission start command
signal STD. A high-speed load 108b that has been directly driven from the main
control circuit unit 120A is indirectly high-speed driven from the combination control circuit unit 130A using the first down-
link data. A low-speed analog input
signal ANL that has been indirectly input to the combination control circuit unit 130A is input to a specific input channel of a multi-channel AD converter 125 in the main control circuit unit 120A via an indirect
multiplexer 115b. By performing channel selection using the down-link communication data DND, the loading of
analog signal is performed without depending on the low-speed up-link communication, and the number of points of a medium-speed analog input signal ANM that has conventionally been directly input to the main control circuit unit 120A is decreased, whereby the number of the input and output terminals of the main control circuit unit is decreased and a decrease in size is achieved.