43 results about "Oscillator sync" patented technology

Synchronization of oscillators based on anharmonic nanoelectromechanical resonators. Experimental implimentation allows for unprecedented observation and control of parameters governing the dynamics of synchronization. Close quantitative agreement is found between experimental data and theory describing reactively coupled Duffing resonators with fully saturated feedback gain. In the synchonized state, a significant reduction in the phase noise of the oscillators is demonstrated, which is key for applications such as sensors and clocks. Oscillator networks constructed from nanomechanical resonators form an important laboratory to commercialize and study synchronization—given their high-quality factors, small footprint, and ease of co-integration with modern electronic signal processing technologies. Networks can be made including one-, two-, and three-dimensional networks. Triangular and square lattices can be made.

The present invention provides methods and apparatus for integrating the operation of a plurality of radio networks. The plurality of radio networks may utilize a common frequency spectrum. The radio center frequencies are adjusted so that frequency drift in relation to each radio network is reduced. Also, system information about the plurality of radio networks may be sent on a radio channel that is associated with one of the radio networks. An oscillator synchronizer synchronizes a first reference oscillator that is associated with a first radio network and a second reference oscillator that is associated with a second radio network in order to adjust radio center frequencies. With a variation of the embodiment, a reference oscillator of one of the radio network adjusts center frequencies for radios that are associated with the other radio network.

A system for synchronizing a second receive chain relative to a first receive chain in a multi-mode communication system. The system includes a first circuit that measures a first frequency associated with the first receive chain. A second circuit adjusts a second frequency associated with the second receive chain based on the first frequency and provides a desired second frequency to the second receive chain in response thereto. In a specific embodiment, the first circuit includes a first counter that receives a signal associated with an output of a first oscillator and provides a measurement of the first frequency in response thereto. The second circuit includes a frequency synthesizer for providing the desired second frequency in response to a frequency control or reference signal. Another circuit generates the control or reference signal based on a difference between the second frequency and the first frequency. A second counter receives a signal characterized by the second frequency and provides the second frequency in response thereto.

This invention synchronizes the sample clocks of an entire wireless network from a single central base station. Unlike a conventional digital radio network where every terminal must have a synchronization circuit in its receiver to adjust the sample clock, each of the radio terminals in this network is clocked from an independent free-running oscillator. For each terminal, the base station learns the frequency and phase of the oscillator by exchanging a special set of signals: first a vernier signal to determine the initial time and frequency offset, and then an early-late signal to track changes in the oscillator. Once the base station is synchronized to the terminal's oscillator, it can determine the absolute path delay between itself and the terminal and correct for the delay using an equalizer. Signals received from the terminal are corrected after the signal arrives at the base station. Signals sent to the terminal are corrected within the base station before they are transmitted so they arrive at the terminal at the precise time that the terminal's free running oscillator takes a sample.

Present-day single or multiple fractional phase-locked loop frequency synthesizers are not phase coherent for they use a digital accumulator modulo a number P with a variable increment K, whose state is a function of the history of the change in values that have been imposed on the increment. This lack of phase coherence rules out the use of these synthesizers in certain fields such as that of Doppler radars. A novel type of single or multiple fractional phase-locked loop frequency synthesizer that is coherent in phase is proposed herein. This type of synthesizer comprises one or more counters with an increment of one, having their rate set by the reference oscillator of the synthesizer and being used in phase memories to enable changes in the increment or increments following a change in the fractional division ratio at instants that are synchronous with the reference oscillator.

A method and apparatus for building a long range RFID system is disclosed. A new signaling structure called Block Pseudo Noise is described that allows for more computationally efficient decoding. A novel approach to synchronize the RFID reader local oscillator with the RFID tag oscillator using an on board GPS receiver on the RFID tags and RFID reader is also disclosed. A novel positioning technique called Asynchronous Time Difference of Arrival used to located RFID tags is also disclosed.

A system, method, and apparatus to facilitate the synchronization of oscillators between members of a Heterogeneous Network (HetNet) to form a self-synchronizing network (SSN). The network members are configured to broadcast information indicative of the reliability of their oscillator. Network members attempt to look for reliable sources such as those originating from a macrocell base station or GPS. If such a source is found, the member cell updates it clock accuracy confidence level number (CACL) to indicate this. Network members also share information regarding the frequency offsets between one another. Every cell member then applies a weighted average function to determine how to update its own oscillator and CACL value accordingly. Cell members can also update their functionality, such as RF power level, in response to varying degrees of CACL values. This operation results in a convergence of all cell members to the most accurate oscillator offset value.

The invention discloses a tunable ultrashort pulse fiber optic parametric oscillator and relates to the fields of parametric oscillators and lasers. The oscillator comprises a tunable laser, an isolator, an intensity modulator, a first amplifier, a filter, a phase modulator, a second amplifier, a first polarization controller, a circulator, a chirped fiber grating, a wavelength division multiplexer, a high-nonlinearity optical fiber, an optical fiber coupler and a second polarization controller. The oscillator adopts a time lens system to compress optical pulse to realize an ultrashort pulse source with tunable repetition frequency and operating wavelength, the repetition frequency is decided by a radio frequency signal applied to a time lens and is very easy to be synchronous to the parametric oscillator. Through utilization of the tunable characteristics of the repetition frequency and the wavelength of the light source of the time lens and combination of time dispersion tuning and pump wavelength tuning mechanism, the fiber optic parametric oscillator can realize the ultrashort pulse laser output at tunable wide working waveband and high pulse quality.

A phased locked loop (PLL) incorporates multiple voltage controlled oscillators including one that operates in a lower frequency range than an operational VCO used by the PLL. A VCO selection circuit allows the system to select from one or more alternate VCOs. A ring oscillator VCO may be used as the alternate VCO for a PLL that uses a LC VCO for the operational VCO. While the ring oscillator VCO provides lower performance, the ring oscillator VCO allows the system with the PLL to be run at a lower speed for testing, debugging or characterization.

A phase lock loop (PLL) is an important component in wireless systems. CMOS technology offers voltage controlled oscillator designs operating at 60 GHz. One of the difficulties is dividing the high frequency clock down to a manageable clock frequency using conventional CMOS. Although injection locked dividers can divide down this clock frequency, these dividers have limitations. A divide by 2 is presented that uses several techniques; feed forward, clock amplification and series peaked inductors to overcome these limitations.

A DC-DC switching converter device (101), in particular a quarter-brick or eighth-brick device having an industry standard pin out, comprises a pulse-width modulation circuit (132) for driving a power converting switch, a trim connector (109) for adjusting an output voltage of the device, where the device (101) is designed such that the pulse-width modulation circuit (132) is synchronizable to an external oscillator by an external synchronization signal applied to the trim connector. A DC-DC converting circuit comprises a plurality of DC-DC switching converters (101) featuring trim connectors (109) for adjusting output voltages of the converters (101), whereby the converters (101) are connected such that they share a common input bus. It further features a system EMI (electromagnetic interference) filter common to all the DC-DC switching converters (101) and an external oscillator delivering an external synchronization signal to the plurality of DC-DC switching converters (101). The external oscillator is designed such that a frequency of the external synchronization signal is higher than a free running frequency of each of the plurality of DC-DC switching converters (101). The external oscillator is connected to the trim connectors (109) of the DC-DC switching converters (101).

The invention discloses a pulse coupled oscillator time synchronization model and method based on firefly synchronization, and belongs to the technical field of wireless network communication. A model introduces a negative coupling factor in a phase coupling mode only with positive coupling, unifies a coupling strength reference, constructs positive and negative different coupling strengths, and divides the phase coupling mode into excitation coupling and inhibition coupling; the variation interval of the oscillator phase is divided in a halving mode, and synchronous tracking is carried out on the oscillator in different initial states. The method comprises the synchronization of two oscillators and the synchronization of two oscillators in the multi-oscillator system, and finally the synchronization of the multi-oscillator system is mapped. According to the model and the method, the phase coupling mode is optimized, the synchronization speed of the system is improved, and certain theoretical guiding significance and application value are achieved for actual production.

In an embodiment of a converter, a first oscillator provides switching signals for switching between charging and discharging of a capacitor, and a second oscillator is configured to add an offset voltage or a feedback-current-dependent voltage to a sawtooth waveform generated by the second oscillator switched in synchronism with the first oscillator.

An auto trimming oscillator includes a Successive Approximation Register (SAR), a frequency detector and an n-bit comparator. The SAR is used to iteratively trim the oscillator output clock frequency based on a difference between a reference clock frequency and the oscillator output clock frequency. The oscillator is trimmed to deliver a clock frequency which is a closest match to the reference clock frequency.

A quadrature VCO includes a first oscillator unit and a second oscillator unit. Each of the first and second oscillator unit is composed of a DC bias source, a complementary cross-coupled pair, an LC resonator unit, a frequency-doubling sub-harmonic coupler unit, and a ground terminal. When the LC resonator units of the first and second oscillator units are operated, four signals of different phases can be outputted via the output terminals. In this way, the output phase difference of the two oscillator units can keep 180 degrees and allow the two oscillator units to mutually inject signals to generate quadrature output signals.

Device and method for temperature compensation in a clock oscillator using quartz crystals, which integrates dual crystal oscillators. The minimal power consumption is achieved through an efficient use of a processor in charge of the synchronisation of the two oscillators. The invention is particularly adapted for the provision of a precise reference clock in portable radiolocalization devices