10 results about "Oscillator sync" patented technology

The embodiment of the invention relates to oscillator synchronization. A circuit includes an injection locked oscillator circuit (402) and a sensing circuit (404). The injection locked oscillator circuit (402) has an input and an output. The sensing circuit (404) includes a sampling circuit (504) and a comparator (506). The sampling circuit (504) has a first input coupled to the input of the injection locked oscillator circuit (402), a second input coupled to an output of the injection locked oscillator circuit (402), and an output. The comparator (506) has an input coupled to the output of the sampling circuit (504), and an output.

Clock monitors for circuits having a plurality of oscillators. The clock monitors produce an error indication when one oscillator is determined to be outside of a desired operating range or beyond a defined threshold with respect to a second oscillator. The clock monitors include a synchronizer configured to receive a clock signal from a first oscillator of the plurality of oscillators and synchronize the received clock signal with a second oscillator and to produce a synchronized clock signal. The clock monitors can include a counter configured to produce a count value based on synchronized clock signal. The clock monitors include comparison circuitry configured to receive the count value and produce an error indication when the count value is outside a predetermined range. The clock monitors may be used to ensure correct clock operation for different transition scenarios, e.g., turning on or off a certain clock or power domain.

Electronic Device for Random Number Generation This description relates to an electronic device (1) comprising: a first ring oscillator (RO1) and a second ring oscillator (RO2); a synchronous flip-flop (FF); a counter (COUNTER); a first circuit (Nm CTRL) configured to modify a period of at least one of the two oscillators (RO1, RO2) so that an average difference between the periods of the two oscillators is equal to a target difference; and a second circuit (PROCESS) configured to: initialize a value of an integer K, calculate sums (VAL) of K successive values ​​of the counter (COUNTER), calculate an Allan variance (VAR) on the calculated sums (VAL), and set K to its current value if the calculated variance is greater than a first threshold and increment K otherwise. Figure for the abstract: Fig. 1

High-precision wireless synchronization can be achieved between multiple devices. [Solution] The synchronization device comprises a control unit, a clock, and a synchronization unit, wherein the clock is equipped with a self-propelled oscillator that acts as a clock source, and the synchronization unit controls its own oscillator to synchronize with an oscillator provided by another synchronization device. Furthermore, the synchronization unit controls the rise time of its own oscillator to synchronize its frequency and phase with an oscillator provided by another synchronization device.

A circuit for implementing ring oscillator synchronous chopping is described herein. The circuit may include a pair of differently arranged ring oscillators, chopping logic, and control logic. The chopping logic is configured to perform a chopping operation of the ring oscillator. The control logic is configured to: stop each ring oscillator in a predefined state; after the two ring oscillators are stopped, chopping logic is started to execute chopping operation; and restarting the two ring oscillators after the chopping operation is completed.

Methods and systems for synchronizing at least one remote local oscillator with a central local oscillator, comprising receiving a remote local oscillator signal from at least one remote local oscillator and a master local oscillator signal from the central local oscillator and in response determining a round-trip phase measurement of temporal delay variability of the duplex real-time link between the remote station and central station, measuring frequency vs. time of the remote local oscillator signal relative to the master oscillator, adjusting the measured frequency vs. time according to the round-trip phase measurement to remove effects of temporal delay variability over the duplex real-time link telemetry, digitally filtering the measured frequency to remove variations in frequency on timescales<10× the round-trip delay and that are known not to be intrinsically due to the remote local oscillator, generating a phase increment signal from the filtered measured frequency, receiving and adjusting the local oscillator signal according to the phase increment signal and in response generating a derived digital domain clock signal that tracks the master local oscillator signal and converting the derived digital domain clock signal to an ultra-low phase-noise time domain voltage clock signal.

Described herein is a circuitry for enabling synchronized chopping for ring oscillators. The circuitry may include a differentially arranged pair of ring oscillators; a chopping logic configured to perform a chopping operation for the ring oscillators; and a control logic configured to: stop each ring oscillator in a predefined state; enable the chopping logic to perform the chopping operation after both ring oscillators are stopped; and restart both ring oscillators after the chopping operation is completed.

A circuit includes an injection locking oscillator circuit and a sense circuit. The injection locking oscillator circuit has an input and an output. The sense circuit includes a sampling circuit and a comparator. The sampling circuit has a first input coupled to the input of the injection locking oscillator circuit, a second input coupled to output of the injection locking oscillator circuit, and an output. The comparator has an input coupled to the output of the sampling circuit, and an output.

The present description concerns an electronic device (1) comprising: a first ring oscillator (RO1) and a second ring oscillator (RO2); a synchronous flip-flop (FF); a counter (COUNTER); a first circuit (Nm CTRL) configured to modify a period of at least one of the two oscillators (RO1, RO2) so that a mean difference between the periods of the two oscillators is equal to a target difference; and a second circuit (PROCESS) configured to: initialize a value of an integer K, calculate sums (VAL) of K successive values of the counter (COUNTER), calculate an Allan variance (VAR) on the calculated sums (VAL), and set K to its current value if the calculated variance is greater than a first threshold and increment K otherwise.

Electronic Device for Random Number Generation This description relates to an electronic device (1) comprising: a first ring oscillator (RO1) and a second ring oscillator (RO2); a synchronous flip-flop (FF); a counter (COUNTER); a first circuit (Nm CTRL) configured to modify a period of at least one of the two oscillators (RO1, RO2) so that an average difference between the periods of the two oscillators is equal to a target difference; and a second circuit (PROCESS) configured to: initialize a value of an integer K, calculate sums (VAL) of K successive values ​​of the counter (COUNTER), calculate an Allan variance (VAR) on the calculated sums (VAL), and set K to its current value if the calculated variance is greater than a first threshold and increment K otherwise. Figure for the abstract: Fig. 1