2results about How to "Improve planarization effect" patented technology

The application relates to a FLASH device and a forming method thereof. The forming method of the FLASH device comprises the following steps: forming a substrate, the substrate comprising a substrate, a plurality of unit structures located above the substrate and an isolation groove located between adjacent unit structures, the unit structure comprising a floating gate and a dielectric layer covering the floating gate; forming a filling layer filling the isolation groove and covering the dielectric layer; forming an auxiliary layer covering the filling layer, the etching selection ratio of the auxiliary layer and the filling layer reaching 1:1; etching back the auxiliary layer and the filling layer at the same etching rate, removing the auxiliary layer and part of the filling layer, and the surface of the remaining filling layer away from the substrate being flush with the surface of the dielectric layer away from the substrate. The application reduces or even avoids the generation of a filling layer sharp corner at the edge of the isolation groove, and eliminates the influence of the filling layer sharp corner on the subsequent deposition of an erasing layer.

The invention discloses a semiconductor structure and a forming method thereof. The method comprises the following steps: providing a substrate, and etching a first surface of the substrate to form a plurality of grooves; sequentially forming a lower pole plate, a dielectric layer and an upper pole plate of the trench capacitor in the trench; a first through hole conductive structure is formed above at least part of the grooves, and the first through hole conductive structure is electrically connected to the lower pole plate in the groove below the first through hole conductive structure and is electrically connected with the metal wire located on the second face of the substrate through the lower pole plate; the first through hole conductive structure and the second through hole conductive structure used for being connected with an upper electrode plate of the groove capacitor can be synchronously formed, and plane capacitors can be prepared in parallel while the groove capacitor is formed. According to the invention, through pre-forming and embedding the through hole conductive structure in the groove etching and capacitor preparation stage, the etching depth required by the subsequent top layer through hole can be obviously shortened, the high aspect ratio etching difficulty and the side wall damage risk are reduced, the metal filling is improved, and the interconnection alignment tolerance and yield are improved; and meanwhile, the method is compatible with the existing planar capacitor and rear-end interconnection process, and is beneficial to the reliability and the process stability of the device.