34results about How to "Improve planarization effect" patented technology

The invention discloses a method for improving a photoetching critical dimension in a groove process. The method comprises the following steps of: 1, spin-coating negative photoresist on the surfaces of a groove and a silicon wafer and then roasting; 2, carrying out exposure and development by using a maskplate with a graph of a groove of a front layer; and 3, spin-coating a bottom antireflection coating (BARC) on a graph formed in the groove and roasting. By the method, the control capacity of the photoetching critical dimension (CD) in the groove process can be improved and a process window can be optimized.

A fabrication system. A plating tool generates a layer of conductive material on a substrate. A polishing tool uses a mechanical mechanism to remove the conductive material from the substrate. A metrology tool measures an electromagnetic signal induced in the conductive material using a non-destructive testing mechanism. A controller, coupled to the polishing and metrology tools, determines residue thickness and removal rate of the conductive material during the polishing process according to the measured electromagnetic signal, and adjusts process parameters for the plating and polishing tools accordingly.

The invention provides a fabrication method of a shallow groove isolation structure and a chemical mechanical grinding method and system. The fabrication method comprises the following steps of 1) measuring a previous value thickness of a target material layer, and determining a first target removal thickness according to the previous value of the target material layer and the thickness of the target material layer maintained after first-stage chemical mechanical grinding; 2) determining theoretical grinding rate according to actual application time of a grinding consumption material; 3) dynamically correcting a grinding parameter according to the first target removal thickness and the theoretical grinding rate, and performing first-stage chemical mechanical grinding on the target materiallayer according to the grinding parameter; and 4) performing second-stage chemical mechanical grinding on the target material layer to achieve removal of second target removal thickness. By the fabrication method, the grinding parameter is determined by collecting the target removal thickness of the target material layer and grinding the actual application time of the grinding consumption material, the planarization effect of grinding is improved, the residue of the target material layer after chemical mechanical grinding is eliminated, and the yield is improved.

The invention relates to the fields of an integrated circuit manufacturing process and layout design, and discloses an integrated circuit layout structure and a manufacturing method thereof. In order to solve the problem of too low thickness of copper metal in a broad-line region of an integrated circuit layout after chemically mechanical polishing in the prior art, the invention provides an integrated circuit layout structure and a preparation method thereof. By regularly drilling holes for broad lines and through chemically mechanical polishing, the thickness of the copper metal of the broad lines is greatly improved, and the thickness of the copper metal on the broad lines and the thin lines is uniform, so the burden of the chemically mechanical polishing is lightened, the planization capacity is improved, the hotspot problems caused by the broad lines are avoided, and the finished product rate is improved.

The invention discloses an interlayer film manufacturing method. The interlayer film manufacturing method comprises the following steps: step one, providing a semiconductor substrate on which a pattern structure of a semiconductor device is formed; step two, forming a first insulating layer on the bottom surface and side surfaces of the pattern spacer and the surface of the pattern structure outside the pattern spacer; step three, forming a second insulating layer to completely fill the pattern spacer and extend outside the pattern spacer; and step four: performing chemical mechanical polishing on the second insulating layer and the first insulating layer with the pattern structure as a stop layer, and forming the interlayer film formed by stacking the first and second insulating layers filled in the pattern spacer. The interlayer film manufacturing method can reduce or eliminate dishing defects on the interlayer film surface at the top of the pattern spacer, can improve the flatness of the entire interlayer film, and can improve the electrical properties of semiconductor devices.

To provide a material which can be formed into a cured film having high solvent resistance, liquid crystal-aligning properties, heat resistance, high transparency and high planarization, and which can be dissolved in a glycol-type solvent and a lactic acid ester-type solvent (which are solvents applicable in the production line for a planarized film of a color filter) in the formation of a cured film from the material. Disclosed is a polyester composition for the production of a thermally cured film, which comprises the following components (A) and (B): (A) a polyester having a constituent unit represented by the formula (1); and (B) an epoxy compound having two or more epoxy groups. (1) wherein A and B independently represent an organic group containing a ring structure.

The present invention provides a material for forming an organic film, containing a compound shown by the following general formula (1), and an organic solvent. In the formula (1), X represents an organic group having a valency of n1 and 2 to 50 carbon atoms, n1 represents an integer of 2 to 10, R₁ represents at least one or more of the following formulae (2) to (4), where l1 represents 0 or 1, and l2 represents 0 or 1. Thus, provided is an organic film material for forming an organic film that has all of high filling property, high planarizing property, and excellent adhesive force to a substrate.

A method of manufacturing an embedded magnetoresistive random access memory including the following steps is provided. A memory cell stack structure is formed on a substrate structure. The memory cell stack structure includes a first electrode, a second electrode, and a magnetic tunnel junction structure. A first dielectric layer covering the memory cell stack structure is formed. A metal nitride layer is formed on the first dielectric layer. A second dielectric layer is formed on the metal nitride layer. A first CMP process is performed on the second dielectric layer to expose the metal nitride layer by using the metal nitride layer as a stop layer. An etch back process is performed to completely remove the metal nitride layer and expose the first dielectric layer. A second CMP process is performed to expose the second electrode. The manufacturing method can have a better planarization effect.

The embodiment of the invention relates to the field of semiconductor manufacturing, and particularly relates to an integrated circuit and a metal interlayer dielectric layer planarization method for the integrated circuit, so as to solve the problems that surface planarization effects of the metal interlayer dielectric layer are poor and reliability of the integrated circuit is influenced as etch-back is carried out on a spin coating glass layer in the prior art. According to the integrated circuit and the metal interlayer dielectric layer planarization method provided by the embodiment of the invention, as ion curing treatment is carried out on two SOG layers respectively, incomplete thickness curing of the two SOG layers can be avoided, and the integrated circuit can be prevented from having a broken layer; as etch-back treatment does not need to be carried out on the second SOG layer, the problem that the surface planarization degree of the metal interlayer dielectric layer is deteriorated as a result of different etch speeds, surface planarization effects of the metal interlayer dielectric layer are improved, and reliability of the integrated circuit is enhanced.

Disclosed is a material which enables pattern formation in an alkaline developer, and shows high solvent resistance, liquid crystal orientation, heat resistance, high transparency, and high planarity after being formed into a cured film, and can be dissolved in a glycol solvent which can be applied to the production line of a planarized film of a color filter while being formed into a cured film. Specifically disclosed is a photosensitive polyester composition for use in forming thermally cured film, containing component (A), component (B), component (C), and component (D): component (A): a modified polyester obtained by reacting a compound having a functional group selected from a glycidyl group and an isocyanate group with a polyester containing a structural unit represented by formula (1); component (B): an epoxy compound having two or more epoxy groups; component (C): an amino group-containing carboxylic acid compound obtained by reacting a diamine compound with dicarboxylic acid dianhydride; and component (D): 1,2-quinone diazide compound. In formula (1), A and B each independently represent an organic group containing a cyclic structure.

The invention relates to a thin film packaging structure, a thin film packaging method and a concave hole design method. The thin film packaging structure comprises a first inorganic packaging layer,an organic packaging layer, and a second inorganic packaging layer; the first inorganic packaging layer is disposed at the lower end of the thin film packaging structure; the upper surface of the first inorganic packaging layer is provided with a plurality of concave holes; the organic packaging layer is arranged on the first inorganic packaging layer; the organic packaging layer is made of organic ink; and the organic packaging layer is formed by coating the organic ink on the first inorganic packaging layer, making the organic ink stand still and flattening the organic ink; and the second inorganic encapsulation layer is disposed on the organic encapsulation layer. According to the thin film packaging structure of the invention, the first inorganic packaging layer is formed, the plurality of concave holes are formed in the first inorganic packaging layer; the plurality of concave holes are designed; the contact angle between the organic ink and the first inorganic packaging layer isreduced by changing the hole diameter of each concave hole and the hole distance between two adjacent concave holes, and therefore, the wettability of the organic ink is improved, and the planarization effect of the organic ink is improved.

The invention discloses a manufacturing method of a shallow trench insulation structure. The manufacturing method comprises the following steps: step 1, forming a hard mask layer on a semiconductor substrate and forming a shallow trench; step 2, forming a first insulating layer on the bottom surface and the side surface of a shallow trench and the surface of the hard mask layer outside the shallowtrench; step 3, forming a second insulating layer to completely fill the shallow trench and extend out of the shallow trench; step 4, performing chemical mechanical grinding on the second insulatinglayer and the first insulating layer by using the hard mask layer as a stop layer, and forming a shallow trench insulation structure formed by superposing the first insulating layer and the second insulating layer which are filled in the shallow trench. According to the invention, the flattening effect of the whole substrate surface can be improved, the disc-shaped defects at the top of the shallow trench insulation structure can be reduced or eliminated, and the CMP efficiency can be improved.

Disclosed are a semiconductor structure and a forming method thereof. The forming method comprises the following steps that a substrate is provided, wherein the substrate comprises a high-resistance device area, and the high-resistance device area is composed of a device area and an edge area; separated virtual pseudo gates are formed on the substrate of the device area and the edge area; and an interlayer dielectric film is formed on the substrate exposed out of the virtual pseudo gates, wherein the interlayer dielectric film covers the tops of the virtual pseudo gates; the interlayer dielectric film is subjected to planarization treatment, so that the residual interlayer dielectric film exposes the tops of the virtual pseudo gates, and the residual interlayer dielectric film serves as aninterlayer dielectric layer. Compared with the scheme that the virtual pseudo gate is not formed, the method has the advantage that in the planarization process in the subsequent formation of the interlayer dielectric layer, the top flatness of the interlayer dielectric layer can be improved, and the problem of top dishing of the interlayer dielectric layer can be improved, so that the performance of the semiconductor structure can be improved.