A simple
instruction set processor preferably utilizes six primary components: a fetch unit, and instruction and address register, a controller / decoder, an
arithmetic logic unit, an address
multiplexer, and a storage
multiplexer. The processor utilizes a
data stream containing within it the address for a subsequent instruction to be executed by the processor, thereby avoiding the need for registers of the type utilized in prior art processors. As a result, the processor utilizes a minimal number of registers to perform its operations. The processor utilizes an
instruction set in which every instruction contains a JUMP to the next instruction. By utilizing JUMPs in every instruction and providing the address to which the processor is to JUMP, there is no need for address counters and register pointers. Also, extremely fast state changes are facilitated the contents of only one register identifying a next address must be saved or restored. By eliminating data registers, data streams of any width may be supported by suitably utilizing a plurality of processor connected in parallel. The
elimination of multiple registers enables the processor to more easily be embedded within memory arrays themselves. The processor preferably utilizes six primary components: a fetch unit, and instruction and address register, a controller / decoder, an
arithmetic logic unit, an address
multiplexer, and a storage multiplexer.