25 results about "Delayed Testing" patented technology

The embodiment of the invention provides a key delay test method and system, and the method comprises the steps: capturing a hardware interrupt signal generated by each physical key response in real time through simulating a preset operation event, measuring first delay time, and evaluating the first delay time according to a preset performance threshold value, analyzing existing potential external interference factors and potential system internal anomalies, adjusting initial test environment parameters, obtaining an optimized test environment, repeatedly simulating operation events, capturing hardware interrupt signals generated by response of each physical key, and calculating average delay time as a response characteristic index of the physical key; predicting the use reliability and the aging effect of the physical key by responding to the change trend of the characteristic index, and generating a trend analysis report; according to the technical scheme provided by the embodiment of the invention, the test precision and reliability are improved, a user can take preventive measures in advance, and service interruption or equipment damage caused by key faults is avoided.

The invention relates to the technical field of time delay testing, and particularly discloses an accurate time service receiving module testing method which comprises the following steps: S1, calculating processing time delay, and generating coordinate points based on the processing time delay; s2, clustering the coordinate points according to the density of the coordinate points, and adjusting the clustering radius to obtain a second cluster; s3, adjusting the second cluster according to the clustering center of the second cluster to obtain a target cluster; and S4, obtaining a coordinate point C closest to the theoretical gravity center of the target cluster, and carrying out the time delay test of the time service receiving module based on the coordinate point C. According to the invention, the time cost consumption of the time service receiving module for the time delay test is reduced.

The invention discloses a standard cell library delay test system and a test method thereof, the test system comprises a primary pulse generator, the clock input end of the primary pulse generator receives a test enable signal and generates a start pulse signal; the clock input end of each stage of trigger is connected to the output end of the previous stage of trigger, and the clock input end of the first stage of trigger receives an operation result of a starting pulse signal and an output signal of the last stage of trigger through a logic OR gate; the test system further comprises a feedback control module including a first phase inverter and a logic AND gate, the first phase inverter negates an output signal of any one trigger in the first three stages of the delay chain and then performs logic AND operation with a global reset signal, and a dynamic reset signal is generated and connected to the reset end of the primary pulse generator. According to the technical scheme, the trigger delay chains connected in series in multiple stages and the feedback control module are designed, an additional reference clock path is not needed, and the circuit area is reduced.

The invention relates to the technical field of CXL, and particularly discloses a time delay test method, device, system, equipment and medium for a CXL unit, and the method comprises the steps: directly receiving and transmitting a message to a to-be-tested computer fast interconnection unit through a computer fast interconnection interface module corresponding to the to-be-tested computer fast interconnection unit through an application message manager, and recording a receiving and transmitting timestamp; the computer fast interconnection interface module comprises a computer fast interconnection root port module and / or a computer fast interconnection terminal interface module, so that the message receiving and transmitting timestamps of the computer fast interconnection unit can be directly obtained based on hardware, and link errors introduced in a system-level test are avoided; direct measurement of the time delay performance of the computer fast interconnection unit is achieved, and therefore accurate testing of the time delay performance of the computer fast interconnection unit is achieved.

The invention discloses a cable transmission time delay test system, which comprises a pulse generation module, a tee joint or circulator, a signal amplification shaping module and a time difference measurement module, and is characterized in that the output end of the pulse generation module is connected with the first port of the tee joint or circulator, and the second port of the tee joint or circulator is electrically connected with a to-be-tested cable; the third port of the tee joint or the circulator is electrically connected with the input end of the signal amplifying and shaping module, and the output end of the signal amplifying and shaping module is electrically connected with the input end of the time difference measuring module. A test pulse signal is injected into the to-be-tested cable through the second port of the tee joint or the circulator, then an echo signal reflected by the tail end of the to-be-tested cable is collected, the time interval between the test pulse signal and the echo signal is measured, and finally the transmission time delay of the to-be-tested cable is calculated according to the time interval. Therefore, the test can be completed only by contacting one end of the cable, the installed equipment does not need to be disassembled, the on-site test process is simplified, and the efficiency is improved.

The invention discloses a link delay test method of a flexible direct-current valve control system and a related device, and the method comprises the steps: determining a link delay type according to a starting point and an end point of a link through which a signal passes; according to the link delay type, determining the type of a test signal for testing the link delay, a test starting point for sending the test signal, a link through which the test signal passes, and a test tool for capturing the test signal after the test signal passes through the link; when the test tool captures the level change of the test signal, recording the moment of the level change; and calculating the link delay of the flexible direct-current valve control system according to the moment of the level change. According to the method, comprehensive and accurate testing of the link delay of the flexible direct valve control system is realized, so that the problem that a special testing method for the link delay of the flexible direct valve control system does not exist in the prior art is solved.

The invention relates to the technical field of artificial intelligence, and provides a large model first word delay test method and device, equipment and a medium, and the method comprises the steps: determining a target large model needing to be tested, and determining a target streaming interface, used for providing service, of the target large model; acquiring a request sending script, and acquiring a delay calculation script; executing a request sending script through the test tool, sending a service request to the target streaming interface, recording a sending moment of the service request, and recording a receiving moment of receiving a first response lexical element returned by the target streaming interface; and executing the delay calculation script through the test tool, and calculating the first word delay of the target large model according to the sending time and the receiving time. The method can be applied to the first word delay test of the large model in the business fields of financial science and technology, medical treatment, health and pension and the like, a new special test tool does not need to be developed, the capacity of an existing test tool can be reused, and the first word delay test of the large model can be achieved at low cost.

According to the TSN end-to-end time delay testing method based on the AS protocol, aiming at a time delay test of an airborne TSN, a TSN end-to-end time delay testing system is established, the TSN end-to-end time delay is calculated through a timestamp in an AS data frame, an ns-level end-to-end time delay result is provided, the accuracy and effectiveness of the TSN end-to-end time delay are ensured, and the TSN end-to-end time delay testing efficiency is improved. The problem of TSN network end-to-end delay test is effectively solved, the accuracy and effectiveness of test data are ensured, and a reference basis is provided for development and test of similar products.

The invention relates to the technical field of an insulation process of data wire production, and discloses an online control method and system of delay test equipment, and the method comprises the steps: constructing a data collection module, a data analysis module, a parameter setting module, a real-time monitoring module and a feedback control module; real-time monitoring and intelligent control of key parameters in the wire production process are achieved, the data acquisition module acquires data and monitors the equipment operation state and environmental conditions, and the data analysis module processes the data through a delay calculation formula and conducts moving average and error correction so as to ensure the data accuracy. The parameter setting module prompts an operator to adjust unreasonable parameters, the real-time monitoring module displays production data and abnormal information, and the feedback control module automatically adjusts equipment parameters and continuously monitors until production returns to normal. The method has the advantages of online real-time monitoring, full-process coverage detection and accurate identification of the axial delay difference.

The invention discloses a method for realizing wired speed measurement through a physical key, and the method comprises the following steps: determining test types which comprise a connectivity test, a performance test and a delay test; collecting historical test data, screening test parameters with the highest use frequency from the historical test data, and searching parameter settings related to the test updated within one month through big data; matching the screened setting parameters of the historical data with the parameters of the big data search, removing the same parameters in the big data search to obtain the recently updated setting parameters, outputting the parameters with the highest use frequency of the historical data and the updated parameters at the same time for an operator to select, and after selection is completed, pressing a physical key to start wired speed measurement. By collecting historical data and big data search data, the obtained test parameters are more comprehensive, and meanwhile, the method also has a speed measurement network card selection function, so that the speed measurement result is more accurate.

The invention provides a deterministic time delay testing device and method, electronic equipment and a storage medium, and belongs to the technical field of high-speed data converter serial interface systems. The testing device comprises a clock source, an ADC, an FPGA and an oscilloscope. Wherein the ADC and the FPGA are respectively connected with the clock source, so that an ADC side system reference clock and an FPGA side system reference clock generated by the clock source can be respectively received, and an ADC side local multi-frame clock and an FPGA side local multi-frame clock which are synchronous are respectively output. The oscilloscope is connected with the clock source, the ADC and the FPGA, so that the oscilloscope can monitor the target time difference obtained by subtracting the rising edge time point of the ADC side system reference clock from the rising edge time point of the FPGA side system reference clock and monitor the absolute value of the rising edge delay difference between the ADC side local multi-frame clock and the FPGA side local multi-frame clock. The deterministic time delay of the serial interface system of the high-speed data converter can be accurately determined through the absolute value of the target time difference and the rising edge time delay difference monitored by the oscilloscope.

This application relates to a power line detection method, apparatus, host computer device, and system. The method includes: sending a delay test command to each acquisition card device to obtain signal time data of the power line under test; sending a fault test command to each acquisition card device to obtain a test signal set of the power line under test; determining the delay test data of the power line under test based on the signal time data; determining the fault test data of the power line under test based on the test signal set; and sending the delay test data and fault test data of the power line under test to a cloud platform, instructing the cloud platform to locate the fault in the power line under test and determine the fault location. This method eliminates the need for segmented detection of the power line under test, thereby improving the fault detection efficiency.

The invention discloses a timestamp verification method, system and device and a computer readable storage medium, and relates to the technical field of network testing, and the method comprises the steps that when a tested network device returns an actual response message, a test platform immediately and dynamically generates a target expected response message based on a time delay test message, a first timestamp for receiving the time delay test message and a second timestamp for sending the time delay test message, monitored by the test platform, of the tested network equipment are injected into the target expected response message, and then the formats and contents of the target expected response message and the actual response message are automatically compared, so that timestamp verification of the tested network equipment is completed; according to the method, the problem of increase of test complexity and time cost caused by manual comparison is solved, and the beneficial effects of improving the development efficiency and quality of logic codes, ensuring the accuracy of timestamp verification and reducing the workload of on-board debugging in the later period are achieved.

The present invention provides a PCIe exchange delay test device and method, which relates to the field of PCIe exchange delay technology. The test device mainly includes a CPU module, a NOC module, a first bridge module, a second bridge module, a memory module, a local time module, a first timestamp adding module, a first calculation module, a second timestamp adding module, a second calculation module, an RC controller module and an EP controller module. The scheme has a simple structure and is easy to operate. After connecting the PCIe exchange chip to be tested, it only needs to write data to the specified address and then read the address to obtain the accurate delay information of the PCIe exchange chip to be tested; the scheme can support the exchange delay measurement of the PCIe exchange chip from the UP port to the DP port or from the DP port to the UP port in two directions; the scheme can also further improve the measurement accuracy by increasing the clock frequency of the counter in the local time module.

The utility model discloses a miniature circuit breaker time-delay test bench. The miniature circuit breaker time-delay test bench comprises a test bench body, the conveyor belt is used for continuously conveying the miniature circuit breaker; the first blocking assemblies are arranged on the two sides of the conveying belt and used for blocking the miniature circuit breaker from continuing to advance; the second blocking assemblies are arranged on the two sides of the conveying belt and located behind the first blocking assemblies, and the second blocking assemblies are used for blocking the miniature circuit breaker from continuing to advance; and the test assembly is located between the first blocking assembly and the second blocking assembly, and the test assembly is used for fixing the miniature circuit breaker and testing the electrical performance of the miniature circuit breaker. Through the above design, the small-sized circuit breaker testing device does not need to be operated by a worker, and a plurality of small-sized circuit breakers can be tested each time, so that large-scale testing of the small-sized circuit breakers is realized, and the product has the advantages of improving the testing efficiency and reducing the manufacturing cost.

This invention discloses a method, apparatus, and system for audio delay testing of a broadcasting system. Based on a response delay test start signal, a delay test signal is generated and sent to a networked broadcasting system, allowing the networked broadcasting system to provide a feedback broadcast test signal. The system receives the broadcast test signal and converts both the broadcast test signal and the delay test signal into broadcast level signals and test level signals, respectively. The delay test result is calculated and output based on the broadcast level signals and test level signals. This invention uses the generated delay test signal as a reference signal for delay testing of the broadcast signal output by the broadcasting system, avoiding delay test errors caused by data transmission of externally acquired reference signals, thus improving the accuracy of delay testing. Directly acquiring the broadcast test signal fed back by the broadcasting system saves data transmission time for audio signal acquisition from the broadcasting system's power amplifier equipment, improving testing efficiency.

The invention provides a PCIe exchange delay testing device and method, and relates to the technical field of PCIe exchange delay. The testing device mainly comprises a CPU module, an NOC module, a first bridging module, a second bridging module, a memory module, a local time module, a first timestamp adding module, a first calculation module, a second timestamp adding module, a second calculation module, an RC controller module and an EP controller module. According to the scheme, the structure is simple, the operation is convenient, and after the tested PCIe exchange chip is connected, accurate delay information of the tested PCIe exchange chip can be obtained only by writing data into a specified address and then reading the address; according to the scheme, the switching delay measurement of the PCIe switching chip in two directions from the UP port to the DP port or from the DP port to the UP port can be supported; according to the scheme, the measurement precision can be further improved by improving the clock frequency of a counter in the local time module.

1. The name of the product of this design: the main body of the photon-to-photon delay test equipment. 2. Purpose of this design product: The whole product is used to detect the PTP delay of XR (VR, AR, MR) products, and the part is used as the main body of the delay test equipment. 3. The design key point of this appearance design product lies in the shape. 4. The picture or photo that best illustrates the key points of the design: Design 1 Stereoscopic drawing 1. 5. Designate Design 1 as the base design. 6. Other situations that need to be explained Other explanations: This patent requests partial design protection: The protected part in the view of design 1 is the part drawn with solid lines, and the part drawn with dotted lines does not constitute the part required to be protected by the local appearance. The portion covered by the blue translucent block in the view of Design 2 does not constitute the portion for which protection is sought for the local appearance.

The invention provides a VR product delay test method and a VR product delay test device, and belongs to the technical field of VR product test. The VR product delay test method comprises the following steps: fixing a calibrated VR product on a mobile structure, and entering a test point; determining an initial origin position; static jitter data of the moving structure and the VR product and static jitter data of the moving structure after the moving structure returns to the starting original point position after track motion are obtained, and the two pieces of obtained static jitter data serve as the error range of VR product motion; controlling the VR product to move, and synchronizing the screen display state transition of the VR product; in the movement process of the VR product, the time from the moment when the VR product returns to the starting original point position to the moment when the screen is converted to the first state is obtained, and the time is the delay time of the VR product. The test cost is low, the precision is high, and the millisecond level can be reached.

The invention discloses a delay test method and device, electronic equipment, a storage medium and a computer program product, and the delay test method comprises the steps: recording the awakening time of a target application program as the processing starting time under the condition that it is monitored that the target application program is awakened for the first time by an input event; when it is monitored that the target application program enters the sleep state, recording the time when the target application program enters the sleep state this time as processing ending time; under the condition that the target application program is not awakened again within a target duration threshold value after the processing ending time, a first duration is determined as the processing delay duration of the input event, and the first duration is the duration between the processing starting time and the processing ending time. The method provided by the invention is not limited by application programs and input events any more, and has very high universality.

The invention discloses a communication time delay optimization method and device, equipment and a storage medium. The method comprises the following steps: periodically sending a time delay test packet to a time delay test service of a receiving end through each link by utilizing the time delay test service of a sending end; when the time delay test service of the receiving end receives the time delay test packet, obtaining the current frame sending time delay, generating a time delay test feedback packet based on the current frame sending time delay and the sending time delay average threshold, and sending the time delay test feedback packet to the time delay test service of the sending end; when the time delay test service of the sending end receives the time delay test feedback packet, the congestion factor of each link is determined according to the current link suggested flow and the corresponding link bandwidth in the time delay test feedback packet; and based on the congestion factor of each link, determining an optimal link for current data transmission by using a flow management module of the sending end and a preset flow migration condition. Compared with the prior art, the communication delay between chips in the vehicle domain controller is effectively reduced.

The application discloses a link delay test method of a flexible direct-current valve control system and a related device, and the method comprises the following steps: determining a link delay type according to a starting point and an ending point of a signal passing through a link; determining a type of a test signal used for testing the link delay, a test starting point for sending the test signal, a link through which the test signal passes, and a test tool used for capturing the test signal after the test signal passes through the link according to the link delay type; recording a time point of a level change when the test tool captures the level change of the test signal; and calculating the link delay of the flexible direct-current valve control system according to the time point of the level change. The method realizes comprehensive and accurate testing of the link delay of the flexible direct-current valve control system, thereby solving the problem that there is no special test method for the link delay of the flexible direct-current valve control system in the prior art.

The invention provides a task switching delay test method, electronic equipment and a storage medium. The method comprises the following steps: creating a test host process; controlling the test host process to execute the following steps: creating a test execution process I; when it is confirmed that the first test execution process is ready, a second test execution process is created; the first test execution process and the second test execution process have the same priority and are independently bound to the same CPU core; obtaining a specified number of task switching time obtained after the first test execution process and the second test execution process execute a preset test rule; calculating the switching time of the specified number of tasks to obtain task switching delay; the task switching delay comprises the maximum value, the minimum value and the average value of the specified number of task switching time. According to the method, the lower limit of task switching delay can be accurately obtained, and basic reference is provided for performance improvement of intelligent driving software or a system.

The application relates to a service performance test method, system, device and medium for 5G industrial application, which comprises the following steps: selecting a corresponding category of 5G industrial application according to obtained service demand, and determining service indexes for the category of 5G industrial application; selecting a network delay test direction or an application delay test direction according to the service indexes and the type of a terminal to be tested; and performing one-way and / or two-way delay test on the terminal to be tested through a pre-set test device and test case in the determined test direction. The application builds a simulated scene meeting the service demand of a customer and close to an actual operation scene according to the customer demand, achieves the purpose of targeted test, and reduces the measurement difficulty. Meanwhile, key index measurement such as delay, bandwidth and reliability is performed in the test, the service performance of the terminal to be tested including timeliness, data volume and system stability is fully considered, and the test efficiency and accuracy are improved.

Transmit, from a first apparatus to a second apparatus, a first indication of a first action to be performed for channel state information, CSI, feedback based on artificial intelligence / machine learning; receive, from the second apparatus, a first response about completion of the first action; and determine a result of a test on the first action based on the first response and a first time length indicating a latency requirement for the first action.