38 results about "Time base generator" patented technology

A predictive time base generator having predictive synchronizer and replica delay element coupled with the synchronizer feedback delay loop. The predictive time base generator receives a clock signal delayed by a predetermined clock delay and produces a predictive time signal advanced in time by an amount represented by the replica delay element. The replica delay element can replicate one or both of a predetermined clock delay and a predetermined data delay, substantially nullifying the respective delays in critical signal paths of a device. The replica delay element can include replicas of structure(s) found in an incoming clock path and an outgoing data path, such elements including, for example, voltage level shifters, buffers or data latches, multiplexers, wire element models, and the like. A predictive computer bus interface adapter which incorporates the aforementioned predictive time base generator also is provided. Such a predictive interface adapter can be adapted to be observant of stringent bus protocol timing budgets imposed under the PCI and PCI-X local bus protocol, and to be robust relative to variations in design and fabrication processes, and environmental operating conditions.

A time base generator and method for providing a first clock signal and a second clock signal comprising generating the first clock signal at a first clock frequency, dividing the first clock frequency by a first integer to produce a first auxiliary signal, dividing the second clock signal by a second integer to produce a second auxiliary signal, generating an error signal by individually weighting and comparing cycle durations or phasing of the first and second auxiliary signals, and generating the second clock signal by a voltage-controlled oscillator controlled by the error signal such that two clock signals of slightly different frequencies with defined time or phase delay are provided.

To provide two clock signals (CLK1, CLK2) of slightly different frequencies (f1, f2) with defined time or phase delay, the first clock signal (CLK1) is generated at the first clock frequency (f1), the first clock frequency (f1) is divided by a first integer (K1) to produce a first auxiliary signal (CLK11), the second clock signal (CLK2) is divided by a second integer (K2) to produce a second auxiliary signal (CLK21), an error signal (ERR) is generated by individually weighting and comparing the cycle durations or phasing of the first and second auxiliary signals (CLK11, CLK21), and said second clock signal (CLK2) is generated by means of a voltage-controlled oscillator (17) controlled by said error signal (ERR).

Systems, apparatus, methods and computer program products are provided for causing a dataframe to be emitted at an air interface of an antenna. A memory stores a transmission to antenna delay value (TAD). An offset calculator calculates an offset value based on an epoch of a global timebase generator and the transmission to antenna delay value (TAD). An interface controller in communication with the offset calculator communicates a segment synchronization signal and a field synchronization signal based on the offset value.

An intelligent lighting control system, a control method, and an intelligent lighting system, the intelligent lighting control system comprising: a main controller, a PWM data buffer controller, and a time base generator, wherein: the main controller is adapted to receive user input the dimming instruction, generate the corresponding target pulse width adjustment parameter according to the dimming instruction, send the target pulse width adjustment parameter to the PWM data buffer controller, and send the PWM wave to the PWM data buffer controller Generate instructions; the PWM data buffer controller is adapted to store the target pulse width adjustment parameters, and when receiving the PWM wave generation instructions, control the time base generator to generate and adjust the target pulse width parameters Corresponding PWM wave; the time base generator is adapted to generate a PWM wave corresponding to the target pulse width adjustment parameter, and input the generated PWM wave to the LED driving circuit. The above-mentioned solution can reduce the demand on the computing performance of the MCU when the LED lighting equipment performs dimming.