26results about "Angle demodulation" patented technology

In some examples, a method includes receiving, at a first device, a radar signal transmitted by a second device at a transmission frequency offset from a local oscillator (LO) frequency of the first device by a target offset and reflected off a target. The method also includes determining an intermediate frequency (IF) of the radar signal based on the transmission frequency and the LO frequency. The method also includes determining a parts per million (ppm) offset between the first device and the second device based on the intermediate frequency and the target offset.

In some examples, a method (300) includes receiving, at a first device, a radar signal transmitted by a second device at a transmit frequency offset from a local oscillator (LO) frequency offset of the first device by a target offset and reflected from a target (304). The method also includes determining an intermediate frequency (IF) of the radar signal based on the transmit frequency and the LO frequency (306). The method also includes determining a fraction per million (ppm) offset between the first device and the second device based on the intermediate frequency and the target offset.

In some examples, a method (300) includes receiving, at a first device, a radar signal transmitted by a second device at a transmission frequency offset from a local oscillator (LO) frequency of the first device by a target offset and reflected off a target (304). The method also includes determining an intermediate frequency (IF) of the radar signal based on the transmission frequency and the LO frequency (306). The method also includes determining a parts per million (ppm) offset between the first device and the second device based on the intermediate frequency and the target offset

The application discloses a signal demodulation circuit and a digital isolation circuit, wherein the signal demodulation circuit is arranged at a receiving end of the digital isolation circuit and comprises a common-gate amplification module, a demodulation module and a common-gate amplification module; the common-gate amplification module is used for receiving full-differential signals output by an isolation module in the digital isolation circuit and amplifying the full-differential signals; the demodulation module is connected with the common-gate amplification module and is used for demodulating the amplified full-differential signals and outputting the demodulated full-differential signals; and the common-gate amplification module comprises a first active load, a second active load, a first NMOS tube, a second NMOS tube, a first coupling capacitor, a second coupling capacitor, a first sampling resistor and a second sampling resistor. The circuit has high anti-interference capability.

An exemplary setup includes: a rectifier circuit arrangement comprising: a first resistor with one terminal; a second resistor with one terminal; a first transistor with a first terminal, a second terminal, and a control terminal; and a second transistor with a first terminal, a second terminal, and a control terminal;a reference circuit arrangement comprising a first input, a second input, a third input, a fourth input and an output, wherein the first input of the reference circuit arrangement is coupled to the control terminal of the first transistor, wherein the second input of the reference circuit arrangement is coupled to the terminal of the second resistor and the first terminal of the second transistor, wherein the third input of the reference circuit arrangement is coupled to the control terminal of the second transistor, and wherein the fourth input of the reference circuit arrangement is coupled to the terminal of the first resistor and the first terminal of the first transistor.

System for processing signals from a gyroscope (102), comprising: at least one drive channel (104) designed to receive an output from a drive axis (110) of the gyroscope (102), wherein the at least one drive channel (104) includes the following: a drive channel analog-to-digital converter (ADC) (112) which receives a drive signal from the drive channel (104) and outputs a digitized drive signal; a drive channel phase-correct demodulator (114) that receives the digitized drive signal and generates a phase-correct demodulated drive signal; at least one drive channel filter (118) that receives the phase-correct demodulated drive signal and outputs a filtered phase-correct demodulated drive signal; and a phase-locked loop (PLL); a detection channel (106) designed to receive an output from a detection axis (108) of the gyroscope (102), wherein the detection channel (106) includes the following: a capture channel ADW (124) that receives an analog rate signal from the capture channel (106) and outputs a digitized rate signal; and a digital signal processor (125) which includes the following: a detection channel phase-correct demodulator (126) that receives the digitized rate signal and generates a phase-correct demodulated rate signal; a capture channel quadrature-phase demodulator (128) that receives the digitized rate signal and generates a quadrature-phase demodulated rate signal; a first acquisition channel filter (130) that receives the phase-correct demodulated rate signal and outputs a filtered phase-correct demodulated rate signal; and a second acquisition channel filter (132) that receives the quadrature-phase demodulated rate signal and outputs a filtered quadrature-phase demodulated rate signal; and a digital subtraction circuit (134) that subtracts the filtered phase-correct demodulated drive signal from the filtered phase-correct demodulated rate signal to generate a sensing axis output signal.

The utility model provides a signal modulation and demodulation system of a digital isolator. The digital isolator and a pulse signal output end and a signal input end of a modulation module are respectively connected with a primary modulation node through a first switch; the first-stage modulation node is connected with the input end of the second-stage modulation node through the phase inverter; the RF signal output end is also connected with the input end of the secondary modulation node; the first switch is controlled by a level signal input by the signal input end to be switched on or switched off so as to control whether the pulse signal and the level signal can reach a primary modulation node for primary modulation or not, and a primary modulation signal is obtained; the secondary modulation node is controlled by the signal flowing out of the primary modulation node to be switched on or switched off so as to control whether the RF signal output by the RF signal output end and the signal flowing out of the primary modulation node can be subjected to secondary modulation or not, and a composite modulation signal is obtained. According to the utility model, two-stage precise modulation control is realized through the arrangement of the two-stage switch, so that the signal modulation precision of the digital isolator is remarkably improved.

Various embodiments relate to a PLL-based FSK demodulator, comprising: a PFD configured to receive an input signal; a fully differential auxiliary charge pump configured to receive and amplify the input signal from the PFD; a capacitor configured to filter the input signal from the auxiliary charge pump; and a fully differential limiter configured to demodulate the input signal and output recovered data.

The present invention discloses a new high-fidelity signal frequency multiplication technology. In the present invention, by directly operating the Fourier expansion coefficients, the accurate maintenance of the waveform and phase characteristics during the signal frequency multiplication process is achieved, and the signal distortion problem caused by spectrum leakage and error accumulation is overcome. Frequency multiplication is directly achieved by matrix operation, without the need for frequency domain transformation and inverse transformation processes, which simplifies the implementation steps of frequency multiplication signal generation and significantly improves calculation efficiency. Through the mathematical design of the frequency multiplication diagonal matrix, it is theoretically possible to support the accurate generation of any frequency multiplication signal without the need for additional spectrum interpolation and expansion operations, thereby eliminating the spectrum interference problem in high frequency multiplication scenarios. Through the matrix-based operation method, the present invention reduces the hardware resource requirements and implementation complexity, making it suitable for deployment in embedded devices or resource-constrained application environments, and has higher economy and scalability.

An apparatus is in a multi-subscriber identity module mode. A first signal in a first plurality of slots associated with a first subscription at a first receiver chain of a downlink pipe and a second signal in a second plurality of slots associated with a second subscription at a second receiver chain of the downlink pipe are received. A difference in timing of a first slot boundary of the first plurality of slots and a second slot boundary of the second plurality of slots is tracked. In response to a change of state of the second receiver chain, a first bandwidth of a direct current (DC) notch filter associated with a DC estimator of the first receiver chain is temporarily increased to a second bandwidth at a same time, prior to, or subsequent to the first slot boundary according to a timing relationship between the first and second boundaries.

A frequency shift keying (FSK) demodulator (100, 200) comprising the following: a frequency estimator (104, 204) based on a digital phase-locked loop (DPLL) configured to convert a phase signal into a frequency signal; a frequency offset estimator (106) that is communicatively coupled to the DPLL-based frequency estimator (104, 204), wherein the frequency offset estimator is configured to estimate and track a direct current (DC) component of the frequency signal; and a mean value filter (108, 208A, 208B) which is communicatively coupled to the frequency offset estimator (106), wherein the mean value filter (208A, 208B) is configured to perform an accumulate-and-discharge operation to improve a signal-to-noise ratio (SNR) at the symbol level of the frequency signal.

In some examples, a method includes receiving, at a first device, a radar signal transmitted by a second device at a transmission frequency offset from a local oscillator (LO) frequency of the first device by a target offset and reflected off a target. The method also includes determining an intermediate frequency (IF) of the radar signal based on the transmission frequency and the LO frequency. The method also includes determining a parts per million (ppm) offset between the first device and the second device based on the intermediate frequency and the target offset.

The present invention discloses a low-noise dual-output synchronous demodulation circuit and method. The synchronous demodulation circuit includes a signal source to be measured, a reference signal source, a pulse generator, a voltage comparator, a logic operator, a reversible counter, a digital-to-analog converter, a digital filter, and an analog filter. A sinusoidal reference signal is generated by the pulse generator as a digital pulse signal. A sinusoidal voltage signal is generated by the voltage comparator and the logic operator as a synchronized pulse count signal. The reversible counter and the digital-to-analog converter are used to obtain a digital voltage signal and an analog voltage signal. Real-time looping is used to maintain the consistency of the voltage value of the sinusoidal voltage signal when the analog voltage signal is synchronized with the digital pulse signal. This synchronous demodulation method can effectively reduce high-frequency components and improve the signal-to-noise ratio of the demodulated signal. The synchronous demodulation circuit can directly provide dual outputs of a digital demodulation signal and an analog demodulation signal.

The present invention discloses a local oscillator circuit for a miniaturized ODU transmission channel, comprising a frequency synthesizer, a frequency multiplier, a local oscillator amplifier and a local oscillator filter connected in series in sequence, wherein the first reference source input end of the frequency synthesizer is electrically connected to an external reference source, the numerical control interface of the frequency synthesizer is electrically connected to a single-chip microcomputer correspondingly, the single-chip microcomputer inputs a frequency control parameter to the frequency synthesizer through the numerical control interface, the frequency multiplier performs a double frequency multiplication on the signal output by the frequency synthesizer to generate a local oscillator signal of a required frequency, and then the local oscillator amplifier performs a power amplification on the local oscillator signal, and then the local oscillator filter suppresses and filters the fundamental wave and the third harmonic in the local oscillator signal. The local oscillator circuit is applied to a satellite communication transmission channel, and can change the required local oscillator signal frequency by parameter configuration, and has the advantages of stability, reliability, power saving, volume reduction, and cost reduction.

Proposed are an LSK demodulator that can implement accurate recovery of a received signal, noise removal, clock synchronization by operating two signal processing means, each of which includes an integrator and a comparator, with a phase difference and a wireless power transmission / sensor information processing device including the LSK demodulator. The LSK demodulator includes an integrating receiver, a quadrature phase clock generator, a finite state machine, a phase interpolator, a duty cycle corrector, and a control circuit.

A reading device for capacitive sensing element comprises a differential capacitive sensing element, a modulator, a charge-voltage conversion circuit, a phase adjustment circuit, a demodulator and a low-pass filter. The modulator outputs a modulation signal to the common node of the capacitive sensing element and modulates the output signal of the capacitive sensing element. The two input terminals of the charge-to-voltage conversion circuit are connected to two non-common nodes of the capacitive sensing element. The charge-to-voltage converter read the output charge of the capacitive sensing element and convert it into a voltage signal. The modulator generates a demodulation signal through the phase adjustment circuit. The demodulator receives the demodulation signal from the phase adjustment circuit and demodulates the output of the charge-to-voltage conversion circuit. The low-pass filter is connected to the output of the demodulator for filtering the demodulated voltage signal to output the read signal.

The invention provides an inductive encoder, and a demodulation circuit and a demodulation method applied to the inductive encoder. The demodulation circuit comprises a clock signal generation circuit, a sampling hold circuit and a low-pass filter circuit. The clock signal generation circuit performs 90-degree phase shift on a signal to be demodulated, and generates a sample hold clock comprising a clock edge and a level hold state. The sampling and holding circuit samples a peak signal of the signal to be demodulated according to the clock edge and holds the peak signal in a level holding state; the amplitude of an envelope signal of a signal to be demodulated is reserved to the maximum extent, amplitude information of a modulation signal is removed to the maximum extent, and then a low-pass filtering circuit is used for carrying out low-pass filtering on a maintained peak signal to form an envelope demodulation signal and outputting the envelope demodulation signal. Compared with the prior art, the envelope demodulation signal obtained after demodulation has the advantages of being large in signal amplitude, small in signal distortion, small in signal delay and the like, and the application requirements of high precision, low delay and low noise of the inductive encoder can be met.

A device includes a baseband processor configured to receive digital samples of a first Wireless Local Area Network (WLAN) signal demodulated with a first Phase-Locked Loop (PLL). The baseband processor is configured to determine whether to switch from demodulating the first WLAN signal using the first PLL to demodulating the first WLAN signal using a second PLL. The device further includes a selection circuit coupled to the first PLL and the second PLL. The selection circuit is configured to switch from the first PLL to the second PLL based on the determination. The baseband processor is configured to receive additional digital samples of the first WLAN signal demodulated with the second PLL.