88 results about "Capacitive storage" patented technology

A storage pixel sensor disposed on a semiconductor substrate comprises a capacitive storage element having a first terminal connected to a fixed potential and a second terminal. A photodiode has an anode connected to a first potential and a cathode. A semiconductor reset switch has a first terminal connected to the cathode and a second terminal connected to a reset potential. A semiconductor transfer switch has a first terminal connected to the cathode and a second terminal connected to the second terminal of the capacitive storage element. A semiconductor amplifier has an input connected to the capacitive storage element and an output. The semiconductor reset switch and the semiconductor transfer switch each have a control element connected to a control circuit for selectively activating the semiconductor reset switch and the semiconductor transfer switch. A light shield is disposed over portions of the semiconductor substrate comprising a circuit node including the second terminal of the semiconductor transfer switch, the second terminal of the capacitive storage element and the input of the semiconductor amplifier and to prevent substantially all photons from entering the circuit node. Structures are present for preventing substantially all minority carriers generated in the semiconductor substrate from entering the circuit node. A plurality of storage pixel sensors are disposed in an array.

A system and related method for a regenerative braking system on a towed vehicle, such as a trailer or semi-trailer. The system provides power and braking to the respective trailer wheels, as needed, to help stabilize the trailer. Power is regenerated during braking. While batteries may be used to store the energy, the system also may use capacitive storage units, which charge and discharge large amounts of energy at a fast rate. A multiple-axis sensor system in conjunction with wheel sensors, load sensors, and proportional control of the brakes and motor power to the axles and wheels, is used to achieve superior load stabilization. The invention can be easily retrofit into new or used trailers, and is self-contained with low maintenance.

A CMOS imaging system with increased charge storage capacitance of pixels yet decreased physical size, kTC noise and active area. A capacitor is linked to the transfer gate and provides a storage node for a pixel, allowing for kTC noise reduction prior to readout. The pixel may be operated with the shutter gate on during the integration period to increase the amount of time for charge storage by a pixel.

A storage pixel sensor disposed on a semiconductor substrate comprises a photodiode having a first terminal coupled to a first potential and a second terminal. A barrier transistor has a first terminal coupled to the second terminal of the photodiode, a second terminal and a control gate coupled to a barrier set voltage. A reset transistor has a first terminal coupled to the second terminal of the barrier transistor, a second terminal coupled to a reset reference potential that reverse biases the photodiode, and a control gate coupled to a source of a RESET signal. A photocharge integration node is coupled to said second terminal of said barrier transistor. The photocharge integration node comprises the control gate of a first source-follower transistor. The first source-follower transistor is coupled to a source of bias current and has an output. A capacitive storage node is coupled to the output of the first source-follower transistor and comprises the control gate of a second source-follower transistor having an output. An exposure transistor is coupled between the output of the first source-follower transistor and a global current-summing node and has a control gate coupled to a saturation level voltage.

A memory device and a method of forming the memory device. The memory device comprises a storage transistor at a surface of a substrate comprising a body portion between first and second source / drain regions, wherein the source / drain regions are regions of a first conductivity type. The storage transistor also comprises a gate structure that wraps at least partially around the body portion in at least two spatial planes. A bit line is connected to the first source / drain region and a word line connected to the gate structure. The memory device does not require an additional capacitive storage element.

A power scheme for an implant on a human or animal body comprises: a charging circuit to provide power to deliver controlled stimulation currents to a body tissue; a capacitive storage arrangement connected with the charging circuit and charged by the charging circuit; a shunting arrangement to limit voltage on the capacitive storage arrangement; a driver array configured to transfer charges from the capacitive storage arrangement to the tissue; and an electrode array connected with the driver array and the tissue.

Driver device and a corresponding driving method for driving a load, in particular an LED assembly comprising one or more LEDs. To provide a better performance, better cost-efficiency, improved power factor and reduced losses, a driver device (1, 1', 2, 2') is provided comprising a rectifier unit (10) for rectifying a received AC supply voltage (VS), load terminals (20) for providing a drive voltage (VL) and / or a drive current (IL) for driving said load, a capacitive storage unit (30) coupled between said rectifier unit and said load terminals for storing electrical energy provided by said rectifier unit and providing electrical energy to said load, and a bridge switching unit (40); coupled between said rectifier unit and said load for switching said capacitive storage unit into a load current path from said rectifier unit to said load terminals with a desired polarity and for switching said capacitive storage unit out of said load current path.

A dynamic random access memory circuit has at least one write bit line, at least one read bit line, a capacitive storage device, a write access device operatively coupled to the capacitive storage device and the at least one write bit line, a sense amplifier operatively coupled to the at least one read bit line and configured to generate an output signal, and a refresh bypass device operatively associated with the sense amplifier and the at least one write bit line so as to selectively pass the output signal to the at least one write bit line.

A method of operating an electrical machine having first and second phase windings. The method includes: (1) applying positive first current to the first phase winding while the first phase winding's back electromotive force (emf) is positive; (2) applying negative second current to the first phase winding while the first phase winding's back emf is negative; and (3) applying positive third current to the second phase winding while the second phase winding's back emf is positive. The first current is conducted through a circuit composed of a battery, the first phase winding, and a first switch. The second current is conducted through a circuit composed of a first capacitive storage element, the battery, the first phase winding, and a second switch, and the third current is conducted through a circuit composed of the battery, the second phase winding, and a third switch.

Driver device and a corresponding driving method for driving a load, in particular an LED assembly comprising one or more LEDs. To provide a better performance, better cost-efficiency, improved power factor and reduced losses, a driver device (1,1′, 2, 2′) is provided comprising a rectifier unit (10) for rectifying a received AC supply voltage (VS), load terminals (20) for providing a drive voltage (VL) and / or a drive current (IL) for driving said load, a capacitive storage unit (30) coupled between said rectifier unit and said load terminals for storing electrical energy provided by said rectifier unit and providing electrical energy to said load, and a bridge switching unit (40) coupled between said rectifier unit and said load for switching said capacitive storage unit into a load current path from said rectifier unit to said load terminals with a desired polarity and for switching said capacitive storage unit out of said load current path.