17 results about "Capacitive storage" patented technology

A data processing system includes a dynamic random access memory (DRAM), a prefetcher, and a refresh controller. The DRAM includes a plurality of DRAM cells, each with a capacitive storage element. The prefetcher is configured to prefetch information from the DRAM into a prefetch buffer in accordance with a prefetch pattern of addresses in the DRAM. The refresh controller includes a dynamic refresh control circuit configured to detect prefetch patterns of the prefetcher, and, in response to a detected prefetch pattern, refresh locations of the DRAM in accordance with a refresh pattern of addresses which is based on the prefetch pattern of addresses.

A new species of capacitive mass energy storage system employing eutectic liquid metallic materials and 2D / 2.5D electrode structures to achieve energy densities capable of replacing battery chemistries as well as petrochemical fuels. The system utilizes metallic bonding principles and submicron-scale electrode separation to sequester high electrical and ionic charge values. Operating at substantially higher voltages than conventional capacitors, the system employs synergistic charge storage mechanisms, and specialized fabrication techniques including capillary printing. Simulations show that the technology provides high energy density simultaneous with rapid charging and near instant discharging capabilities, configurable power output in DC or AC forms, and thermal stability at elevated temperatures. Applications include electric vehicles, autonomous robotics, and medical devices, among others.

Technologies for dual-stage charge collection and energy storage include an energy storage module having a first stage energy storage device, a second stage energy storage device, and a microcontroller. The first stage energy storage device may include capacitive storage and the second stage energy storage device may include battery storage. When rectified input power is available from an unbalanced peak alternating current power signal, the microcontroller activates quick charging of the first stage energy storage device. When the first stage energy storage device is full, the microcontroller activates charging of the second stage energy storage device. When the second stage energy storage device is full, the microcontroller activates power delivery to an external load. Other embodiments are described and claimed.

A dynamic random access memory (DRAM) includes a plurality of main bit cells, a first set of write bit lines, a first set of write word lines, a plurality of canary cells, a second set of write bit lines, and a second set of write word lines. Each main bit cell has a capacitive storage element and is coupled to a corresponding write bit line of the first set of bit lines and a corresponding write word line of the first set of write word lines. The plurality of canary cells are configured to be more susceptible to leakage currents as compared the plurality of main bit cells. Each canary cell has a capacitive storage element and is coupled to a corresponding write bit line of the second set of bit lines and a corresponding write word line of the second set of write word lines.

A data processing system includes a dynamic random access memory (DRAM), a prefetcher, and a refresh controller. The DRAM includes a plurality of DRAM cells, each with a capacitive storage element. The prefetcher is configured to prefetch information from the DRAM into a prefetch buffer in accordance with a prefetch pattern of addresses in the DRAM. The refresh controller includes a dynamic refresh control circuit configured to detect prefetch patterns of the prefetcher, and, in response to a detected prefetch pattern, refresh locations of the DRAM in accordance with a refresh pattern of addresses which is based on the prefetch pattern of addresses.

A vehicle system comprises a powertrain system with one or more electrical loads and a main drive designed to power one or more mechanical loads. A power converter is designed to supply energy to the one or more electrical loads via a main output and an auxiliary output.The power converter comprises a rectifier designed to supply power to the main output and a plurality of switching devices, an inductive-capacitive network operatively coupled to the plurality of switching devices and designed to recover energy from electrical transients generated by the operation of the plurality of switching devices, and a capacitive storage device designed to store the energy recovered by the inductive-capacitive network and to supply a DC / DC converter with this energy, the DC / DC converter being operatively coupled to the auxiliary output.

A capacitance memory cell includes an electrode, a tunnel barrier layer in direct contact with the electrode, a charge trapping layer in direct contact with the tunnel barrier layer, a ferroelectric layer in direct contact with the charge trapping layer, and another electrode in direct contact with the ferroelectric layer.

A data processing system includes a dynamic random access memory (DRAM), a prefetcher, and a refresh controller. The DRAM includes a plurality of DRAM cells, each with a capacitive storage element. The prefetcher is configured to prefetch information from the DRAM into a prefetch buffer in accordance with a prefetch pattern of addresses in the DRAM. The refresh controller includes a dynamic refresh control circuit configured to detect prefetch patterns of the prefetcher, and, in response to a detected prefetch pattern, refresh locations of the DRAM in accordance with a refresh pattern of addresses which is based on the prefetch pattern of addresses.

A capacitive memory cell includes an electrode, a tunneling barrier layer in direct contact with the electrode, a charge trapping layer in direct contact with the tunneling barrier layer, a ferroelectric layer in direct contact with the charge trapping layer, and another electrode in direct contact with the ferroelectric layer.

The present disclosure provides a method for operating a ferroelectric field effect transistor (FeFET) as a capacitive memory device. The method comprises connecting a source terminal and a drain terminal of the FeFET together, applying a small-signal voltage to a gate terminal of the FeFET at zero direct-current gate voltage, and measuring capacitance between the gate terminal and the connected source and drain terminals to determine a capacitance state of the FeFET. The capacitance state corresponds to either a high capacitance state or a low capacitance state based on polarization of a ferroelectric gate stack of the FeFET. The disclosure also provides a FeFET device configured for capacitive memory operation comprising a semiconductor channel, a ferroelectric gate stack disposed over the semiconductor channel, a gate terminal connected to the ferroelectric gate stack, a source terminal and a drain terminal connected to the semiconductor channel, and a body terminal. The FeFET device is configured to operate in a capacitive read-out mode where capacitance is measured between the gate terminal and connected source and drain terminals at zero direct-current gate voltage to determine a memory state.

Various aspects relate to a memory cell including: a field-effect transistor structure, the field-effect transistor structure including a gate structure to control a current flow in a channel, the gate structure including a gate isolation and a floating gate, wherein at least a part of the gate structure extends from a surface of a semiconductor layer into the semiconductor layer; and a capacitive memory structure, the capacitive memory structure including at least two electrodes and a spontaneously polarizable layer disposed between the at least two electrodes, wherein one of the at least two electrodes is in direct physical contact with the floating gate of the field-effect transistor structure, and wherein the spontaneously polarizable layer is disposed over the surface of the semiconductor layer.

The invention discloses a capacitive storage and calculation integrated processing system, method and device and a storage medium, and relates to the technical field of integrated circuits, and the system comprises the steps: carrying out the digital-to-analog conversion processing of digital input data, obtaining a plurality of analog effective input signals and effective weight data, and obtaining reference voltages of different values; the data calculation sub-module obtains a plurality of analog output voltages, sets a screening threshold value, obtains a numerical value obtained by multiplying the reference voltage by the screening threshold value, screens out the analog output voltages which are greater than or equal to the numerical value obtained by multiplying the reference voltage by the screening threshold value, accumulates the plurality of screened analog output voltages and solves an average value; and then the target analog output voltage is transmitted to the output module for analog-to-digital conversion processing to obtain output data. The system combines the characteristics of high energy efficiency of analog calculation and easy expansion of digital calculation, and then introduces reference voltage, so that the precision of output data can be improved.

Various aspects relate to a memory cell arrangement including: bitlines; wordlines; platelines; capacitive memory cells, wherein each of the capacitive memory cells is connected to and selectively addressable by a corresponding bitline, a corresponding wordline, and a corresponding plateline; a control circuit configured to carry out a read-out operation to read a memory state of a capacitive memory cell, the read-out operation including: charging the corresponding bitline to a first characteristic voltage by applying a plateline voltage having a first plateline voltage value at the corresponding plateline and by applying a wordline voltage at the corresponding wordline; decreasing the plateline voltage from the first plateline voltage value to a second plateline voltage value to thereby discharge the corresponding bitline from the first characteristic voltage to a second characteristic voltage; and determining the memory state of the capacitive memory cell based on sensing the second characteristic voltage.

A dynamic random access memory (DRAM) includes a plurality of main bit cells, a first set of write bit lines, a first set of write word lines, a plurality of canary cells, a second set of write bit lines, and a second set of write word lines. Each main bit cell has a capacitive storage element and is coupled to a corresponding write bit line of the first set of bit lines and a corresponding write word line of the first set of write word lines. The plurality of canary cells are configured to be more susceptible to leakage currents as compared the plurality of main bit cells. Each canary cell has a capacitive storage element and is coupled to a corresponding write bit line of the second set of bit lines and a corresponding write word line of the second set of write word lines.

Various aspects relate to a memory cell, the memory cell including: a field-effect transistor structure; and a capacitive memory structure; wherein the field-effect transistor structure and the capacitive memory structure are configured to form a capacitive voltage divider; wherein the capacitive memory structure includes: a first electrode layer, a second electrode layer, and a memory element structured to have at least a first region extending from the first electrode layer to the second electrode layer and a second region extending from the first electrode layer to the second electrode layer, wherein the first region consists of a first material, wherein the second region consists of a second material, and wherein the first material is different from the second material.

Capacitive Electrical Energy Storage System The invention relates to a capacitive electrical energy storage system comprising: a liquid electrolyte; a positive electrode comprising: a first substrate made of conductive material; a first two-dimensional or three-dimensional conductive nanostructure extending over the substrate; and an insulator comprising at least one layer of dielectric material conforming to the shape of the first conductive nanostructure; and a negative electrode comprising: a second substrate made of conductive material; a second two-dimensional or three-dimensional conductive nanostructure extending over the substrate; Figure for the abstract: Fig. 1