69results about "Dual purpose resist" patented technology

A semiconductor bear chip having a bump subjected to high temperatures is pressed, from the upper side, onto a wiring board including a wiring pattern, a thermosetting resin film covering an electrode area on the wiring pattern and having insulating particles dispersed and included and a thermoplastic resin film covering the thermosetting resin film, while applying a ultrasonic wave, thereby inserting the bumps of the semiconductor bear chip through the thermoplastic resin film and the thermosetting resin film to bond the top end portion of the bump with the electrode area.

An object of the present invention is to provide a process for producing a printed wiring board, which is advantageous not only in that the reduction in size and increase in density of the wiring board are achieved and further the steps are simplified, but also in that the connection reliability of mount parts and the yield are improved, and a photosensitive resin composition used in the process. The present invention is directed to a process for producing a printed wiring board, comprising the steps of: (i) forming a solder resist on a wiring board having a circuit; (ii) laminating a preliminarily molded layer of a photosensitive resin composition on the solder resist; (iii) subjecting the layer of the photosensitive resin composition to exposure and development to form a resist pattern of the photosensitive resin composition; (iv) subjecting the entire surface of the resultant board to electroless plating, and (v) stripping the layer of the photosensitive resin composition, wherein the steps are conducted in this order, as well as a photosensitive resin composition and the layer thereof used in the process.

An electronic device substrate having: a base material formed of a thin board; an electrical insulation layer formed on the base material and having plural openings in a thickness direction thereof; and a metal plating layer filled in the plural openings. The base material has a metal layer, a release layer formed contacting the metal layer, and a metal film formed contacting the release layer.

An aspect of the present invention features a method for manufacturing a substrate having a cavity. The method can comprises: (a) forming an upper layer circuit on an upper seed layer; (b) laminating a dry film on a portion of the upper seed layer where a cavity is to be formed; (c) fabricating an upper outer layer by forming an insulation layer on top of the upper seed layer and on top and sides of the upper layer circuit; (d) stacking the upper outer layer on one side of a core layer where an internal circuit is formed; (e) removing the upper seed layer; and (f) forming the cavity by removing the dry film. The method for manufacturing a substrate with a cavity according to the present invention can reduce the total thickness of the substrate while the thickness of an insulation layer remains the same, by forming the insulation layer on sides of an external circuit.

According to embodiments of the present invention, a method for manufacturing a pattern of conductive elements on a substrate is provided. The method includes applying a coating layer of electrically conductive transparent compounds onto a substrate; depositing in a vacuum deposition chamber an electrically conductive material onto the coating layer to form an electrically conductive layer; applying an etch-resist material on selective areas of the electrically conductive layer, wherein the selective areas are substantially areas pre-designed to carry the conductive objects; and chemically etching the electrically conductive material from exposed areas of the electrically conductive layer that are not covered by the etch-resist material.

To provide a wiring substrate which can prevent short circuit between connection terminals, and which realizes reduction of the pitch between the connection terminals. The wiring substrate of the present invention includes a layered structure including one or more insulation layers and one or more conductor layers, and the wiring substrate is characterized in that a plurality of connection terminals are formed on the layered structure so as to be separated from one another; a filling member is filled between the connection terminals; and each of the connection terminals has a side surface composed of a contact surface which is in contact with the filling member, and a spaced surface which is not in contact with the filling member and which is located above the contact surface and below the top surface of the filling member.

A wiring board according to the present invention includes a wiring part formed of one or more layers, a first terminal area disposed on one side of the wiring part in a projecting manner, and a second terminal area disposed on the other side of the wiring part. A resist having an opening for a first terminal area is formed on a surface of a composite made of a plurality of metal layers. A part of a first metal layer of the composite is etched through the opening for a first terminal area to form a hole. The hole is subjected to an electroless plating through the opening of the resist. Thus, the hole is filled with an electroplated layer to form a first terminal area. Then, the resist is removed from the composite, and a wiring layer is formed thereon. Subsequently, a solder resist having an opening for a second terminal area is disposed on the wiring layer. The opening of a second terminal area of the solder resist is subjected to an electroplating so as to form a second terminal area. Removing remaining parts of the composite, a wiring board is completed.

The present invention provides a chip part manufacturing method comprising a separating process capable of suppressing deformation of chip parts, and also provides chip parts. It comprises a step of forming a plurality of frame-like void portions (32) in one main surface of substrate (30) and insulating resin layer (20) having a spiral void portion (40) disposed in the region thereof, a step of forming metal layer (36) in frame-like void portion (32) and spiral void portion (40) and on insulating resin layer (20), a step of polishing metal layer (36) at least up to the upper surface of insulating resin layer and forming coil section (18) in spiral void portion (40), and a step of forming a metal layer for connecting chip parts to frame-like void portion (32), wherein the metal layer is melted and removed by using an etching agent to separate a plurality of chip parts connected to each other by a frame-like connection.