Patents
Literature
Patsnap Copilot is an intelligent assistant for R&D personnel, combined with Patent DNA, to facilitate innovative research.
Patsnap Copilot

49results about How to "Complex function" patented technology

Self supporting three dimension device and preparation method thereof

The invention discloses a self supporting three dimension device and a preparation method thereof. The preparation method of the self supporting three dimension device includes: S1, providing a self supporting insulation dielectric film with a basically flat upper surface; S2, generating a conducting layer and at least one device unit with a preset pattern on the upper surface of the self supporting insulation dielectric film so as to generate a composite layer structure; S3, cutting the composite layer structure so as to obtain at least one suspension portion locally connected with the composite layer structure, wherein each suspension portion is provided with each corresponding device unit; S4, using an ion beam to irradiate the at least one suspension portion so as to deform the conducting layer, and thereby driving each suspension portion to bend around a portion of each suspension portion, connected with the composite layer structure, towards the direction far away from the self supporting insulation dielectric film; S5, removing at least a portion of the conducting layer so as to obtain the self supporting three dimension device. The preparation method of the self supporting three dimension device can prepare a three dimensional structure and micron and nanometer devices which are insulated from one another on the self supporting insulation dielectric film, and has the advantages of being good in controllability, low in cost, and capable of preparing the self supporting three dimension device large in area.
Owner:INST OF PHYSICS - CHINESE ACAD OF SCI

Chip packaging structure and method

An embodiment of the invention discloses a chip packaging structure and method. The structure comprises a substrate base board, a first rerouting layer, a second rerouting layer and at least one inverted chip, the substrate base board comprises a first side surface and a second side surface, at least one through hole is formed in the substrate base board and penetrates the first side surface and the second side surface, first conducting posts are arranged in the through holes, the first rerouting layer is arranged on the first side surface of the substrate base board and electrically connected with the first conducting posts, the second rerouting layer is arranged on the second side surface of the substrate base board and electrically connected with the first conducting posts and first external connection projections, the inverted installation chips are arranged on one side of the first rerouting layer far away from the substrate base board, and second corresponding conducting posts are arranged on electrodes of the inverted chips and electrically connected with the first rerouting layer. According to the method, high-integration density of chips is achieved, input/output device interfaces in the unit area of the chips are increased, and electrical properties of the chips are improved.
Owner:NAT CENT FOR ADVANCED PACKAGING
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products