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48results about How to "Full use of computing power" patented technology

Power network planning construction method based on network reconstruction and optimized load-flow simulating calculation

The invention relates to a power network planning construction method based on network reconstruction and optimized load-flow simulating calculation. The power network planning construction method based on the network reconstruction and the optimized load-flow simulating calculation comprises the steps that load-flow of a power system is calculated by a digital simulation module in a power network simulation platform, constraint of a future power network is set by an operator, interface service calls used for power network planning are increased, a network reconstruction subsystem obtains power network data, rules followed by the network reconstruction subsystem in calculation are determined, calculation constraint is determined, the network reconstruction subsystem acquires an optimal solution, artificial interfering correction is conducted to a network reconstruction result, the result is written into the power network simulation platform, an optimized load-flow subsystem obtains power network data, constraint is determined before the calculation of the optimized loading-flow subsystem, optimized load-flow calculation is developed, the result is exported and sent to the power network simulation platform, artificial interfering correction is conducted to the exported result, and the result after the artificial interfering correction is stored in the power network simulation platform. The power network planning construction method based on the network reconstruction and the optimized load-flow simulating calculation largely improves the working efficiency of power network planning and the efficiency of a power network operation mode, and thus a power network planning working process which is convenient and high in efficiency is created.
Owner:STATE GRID TIANJIN ELECTRIC POWER +2

Ultra high speed ultrasonic imaging device and method based on central processing unit (CPU) + graphic processing unit (GPU) isomeric framework

InactiveCN104688273AMake full use of back-end processing capabilitiesImprove performanceBlood flow measurement devicesInfrasonic diagnosticsSonificationData acquisition
The invention discloses an ultra high speed ultrasonic imaging device and method based on a central processing unit (CPU) + a graphic processing unit (GPU) isomeric framework. An FPGA control probe transmits multi-angle plane wave ultrasonic signals to biological texture to be detected and conducts analog-to-digital conversion and pre-amplification on received data. A large amount of data subjected to preprocessing are transferred into a CPU through a high speed PCI e channel. Data beam forming is achieved in the CPU, and functions like human-computer interaction are achieved. GPU reads data in the inner storage of the CPU, and utilizes the parallel calculation capability and variable frame rate plane wave composite technology to combine and demodulate signals to further achieve super speed imaging. By means of the device and the method, the high-integrity transmitting and receiving scheme and the unified data collection framework are adopted to simplify the front end, the beam forming module is moved to the rear end, the front end is further simplified, the rear end processing capability is fully utilized, and the system performance is improved.
Owner:HARBIN INST OF TECH

Quick medical ultrasonic image system for multiple MV high-definition algorithms based on GPU

The invention discloses a quick medical ultrasonic image system for multiple MV high-definition algorithms based on a GPU. The system comprises an initial starting module, an analog simulation module,an algorithm imaging module and a result display module, wherein the initial starting module completes system initialization setting and the calls the algorithm imaging module for imaging, the analogsimulation module serves as an auxiliary module to produce analog data to be used for other modules, the analog simulation module is a core module of the whole system and receives parameter settingsfrom the initial starting module and data of the analog simulation module or a data acquisition device for imaging calculation, and the result display module conducts last processing and display on the results of other modules and finally achieves quick imaging functions of the multiple MV algorithms. The quick medical ultrasonic image system can complete completed calculation of high-definition medical ultrasonic image algorithms within very short time, used GPU programming for the MV high-definition algorithms can be conveniently deployed on a computer with the GPU, and the quick medical ultrasonic image system can effectively meet the use demand and is good in practicability.
Owner:SOUTH CHINA UNIV OF TECH

Embedded real-time high-definition medical ultrasound imaging system of integrated graphics processing unit

The invention discloses an embedded real-time high-definition medical ultrasound imaging system of an integrated graphics processing unit. The system adopts embedded equipment of the integrated graphics processing unit for achieving medical ultrasound imaging, by adopting an improved high-definition imaging algorithm, the calculation process is suitable for a computing environment of the graphics processing unit, and therefore the image quality of medical ultrasound imaging is improved, and the imaging frame rate of medical ultrasound imaging is increased. Compared with a traditional portable medical ultrasound imaging system, the adopted integrated graphics processing unit embedded system has a high parallel computing capacity, complicated calculation of the high-definition medical ultrasound imaging algorithm can be completed within a short period of time, and real-time high-definition medical ultrasound imaging can be presented. Accordingly, the phenomenon that minimum variance wave beams form high-definition ultrasound imaging is achieved, and a high-definition medical ultrasound image is output in real time on the embedded system. The embedded system of the integrated graphics processing unit is low in price, high in practicability and high in cost performance.
Owner:SOUTH CHINA UNIV OF TECH

Power network planning construction method based on network reconstruction and optimized load-flow simulating calculation

The invention relates to a power network planning construction method based on network reconstruction and optimized load-flow simulating calculation. The power network planning construction method based on the network reconstruction and the optimized load-flow simulating calculation comprises the steps that load-flow of a power system is calculated by a digital simulation module in a power network simulation platform, constraint of a future power network is set by an operator, interface service calls used for power network planning are increased, a network reconstruction subsystem obtains power network data, rules followed by the network reconstruction subsystem in calculation are determined, calculation constraint is determined, the network reconstruction subsystem acquires an optimal solution, artificial interfering correction is conducted to a network reconstruction result, the result is written into the power network simulation platform, an optimized load-flow subsystem obtains power network data, constraint is determined before the calculation of the optimized loading-flow subsystem, optimized load-flow calculation is developed, the result is exported and sent to the power network simulation platform, artificial interfering correction is conducted to the exported result, and the result after the artificial interfering correction is stored in the power network simulation platform. The power network planning construction method based on the network reconstruction and the optimized load-flow simulating calculation largely improves the working efficiency of power network planning and the efficiency of a power network operation mode, and thus a power network planning working process which is convenient and high in efficiency is created.
Owner:STATE GRID TIANJIN ELECTRIC POWER +2

Multi-modal massive-data-flow scheduling method under multi-core DSP

The invention discloses a multi-modal massive-data-flow scheduling method under a multi-core DSP. The multi-core DSP includes a main control core and an acceleration core. Requests are transmitted between the main control core and the acceleration core through a request packet queue. Three data block selection methods of continuous selection, random selection and spiral selection are determined onthe basis of data dimensions and data priority orders. Two multi-core data block allocation methods of cyclic scheduling and load balancing scheduling are determined according to load balancing. Datablocks selected and determined through a data block grouping method according to allocation granularity are loaded into multiple computing cores for processing. The method adopts multi-level data block scheduling manners, satisfies requirements of system loads, data correlation, processing granularity, the data dimensions and the orders when the data blocks are scheduled, and has good generalityand portability; and expands modes and forms of data block scheduling from multiple levels, and has a wider scope of application. According to the method, a user only needs to configure the data blockscheduling manners and the allocation granularity, a system automatically completes data scheduling, and efficiency of parallel development is improved.
Owner:XIAN MICROELECTRONICS TECH INST

Multi-agent traffic simulation parallel computing method and device

The invention discloses a multi-agent traffic simulation parallel computing method, which uses a multi-thread parallel computing mode to carry out path optimization, state updating and simulation data storage and display on an agent vehicle, can calculate road impedance according to real-time road conditions, calculates and updates the optimal path of the vehicle in combination with vehicle attributes, the thread distribution can be adjusted according to the actual calculation time consumption, and the thread load is balanced. The invention further discloses a multi-agent traffic simulation parallel computing device, individual differences of different simulation vehicles are fully considered, common simulation vehicles and intelligent vehicles capable of carrying out information interaction are supported, a multi-thread parallel computing mode is used, the CPU computing power of equipment can be fully exerted, the simulation efficiency is improved, and dynamic path planning can be realized, so that the simulation result better fits the actual situation. The method can be used for researching vehicle behaviors, predicting traffic flow states and testing management and control measures, and help is provided for relieving traffic congestion, reducing traffic hidden dangers and reducing resource waste.
Owner:SOUTHEAST UNIV

Convolution calculation data reuse method based on heterogeneous many-core processor

ActiveCN112559197AImprove data reuseReduce memory access requirementsInterprogram communicationPhysical realisationEngineeringConvolution
The invention discloses a convolution calculation data reuse method based on a heterogeneous many-core processor. A CPU completes convolution calculation of a data block C through a data block A and adata block B. The method comprises the following steps: S1, according to the number of cores of the heterogeneous many-core processor, performing two-dimensional mapping into N * N, dividing the datablock A, the data block B and the data block C into N * N blocks, enabling the (i, j)th kernel to read the (j, i)th block data from the memory into the own on-chip memory, wherein convolution calculation of the data block C (i, j) needs a data block A (i, k) and a data block B (k, j), and k = 1, 2,..., N; and S2, entering a cycle k for N cycles from 1 to N, and completing the Kth convolution calculation of the data block C by using the obtained data block A and data block B. The memory access requirement of convolution calculation on the heterogeneous many-core processor is remarkably reduced, and the many-core calculation capability is fully exerted, so that the high performance of convolution calculation is realized, and the calculation performance of convolution calculation on the heterogeneous many-core processor is improved.
Owner:JIANGNAN INST OF COMPUTING TECH

A robot intelligent self-following method, device, medium, and electronic equipment

The invention discloses a robot intelligent self-following method, device, medium, and electronic equipment. The intelligent self-following method includes the steps of: performing quantization processing on the i-th line point cloud data obtained by multi-line lidar single-frame scanning to obtain The average value of the point cloud data located between two adjacent quantile points is taken as the quantile value Ω; use DBSCAN to perform point cloud clustering on the i-th line point cloud data, and obtain the smallest value λi in the i-th line point cloud data ;Repeat the above steps to obtain n λi of the multi-line laser radar, and then take the average value λ of n λi as the detection result of the multi-line laser radar single-frame scan; calculate the average of the current single-frame scan and the previous historical single-frame scan Euclidean distance d of the value λ and judge whether the target is lost. The present invention is applicable both day and night, and has little impact on the environment; during the following process, the tracking result of the operator is obtained by using the multi-line laser radar, and the detection accuracy is high, and the tracking accuracy is high when combined with the historical track.
Owner:广东盈峰智能环卫科技有限公司 +1

A multi-modal scheduling method for massive data streams under multi-core DSP

The invention discloses a multi-modal massive-data-flow scheduling method under a multi-core DSP. The multi-core DSP includes a main control core and an acceleration core. Requests are transmitted between the main control core and the acceleration core through a request packet queue. Three data block selection methods of continuous selection, random selection and spiral selection are determined onthe basis of data dimensions and data priority orders. Two multi-core data block allocation methods of cyclic scheduling and load balancing scheduling are determined according to load balancing. Datablocks selected and determined through a data block grouping method according to allocation granularity are loaded into multiple computing cores for processing. The method adopts multi-level data block scheduling manners, satisfies requirements of system loads, data correlation, processing granularity, the data dimensions and the orders when the data blocks are scheduled, and has good generalityand portability; and expands modes and forms of data block scheduling from multiple levels, and has a wider scope of application. According to the method, a user only needs to configure the data blockscheduling manners and the allocation granularity, a system automatically completes data scheduling, and efficiency of parallel development is improved.
Owner:XIAN MICROELECTRONICS TECH INST
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