This application provides a monolithic 3D integrated
chip, relating to the field of
semiconductor technology, primarily addressing the problem that current
resistive random access memory (RRAM)-based logic architectures remain relatively fixed and lack flexible
reconfigurability. The monolithic 3D integrated
chip includes a logic layer, a memory computing layer, and a reconfigurable layer stacked sequentially, with interconnections between these
layers. The logic layer transmits computation signals and data to the memory computing layer and configuration data and signals to the reconfigurable layer. The memory computing layer, under the control of the computation signals, performs
matrix multiplication or addition on the computation data and outputs the computation results. The reconfigurable layer, under the control of the configuration signals, performs reconfigurable
processing on the computation results according to the configuration data. This application endows the
chip with flexible programmability and
reconfigurability.