Patents
Literature
Patsnap Eureka AI that helps you search prior art, draft patents, and assess FTO risks, powered by patent and scientific literature data.

2results about How to "Stable throughput" patented technology

Input and output scheduling method and device, electronic equipment and storage medium

The invention discloses an input and output scheduling method and device, electronic equipment and a storage medium, and relates to the technical field of computers.According to the input and output scheduling method and device, the future load state of a storage system is predicted based on historical input and output request data, and the response sequence and the resource allocation strategy of requests with different priorities are dynamically adjusted accordingly; therefore, a mapping relation between load prediction and storage medium characteristics is established, so that the technical problems that key request delay is uncontrollable and system throughput fluctuates when the load suddenly increases in a mixed read-write load scene can be solved; the technical effects of ensuring the low-delay response of the key request, stabilizing the system throughput and improving the overall performance and stability of the system are achieved.
Owner:JINAN INSPUR DATA TECH CO LTD

Monolithic 3D integrated chip

PendingCN122086834AFlexible and programmableFlexible and reconfigurable capabilitiesDigital storageArchitecture with single central processing unitComputer architectureLogical layer
This application provides a monolithic 3D integrated chip, relating to the field of semiconductor technology, primarily addressing the problem that current resistive random access memory (RRAM)-based logic architectures remain relatively fixed and lack flexible reconfigurability. The monolithic 3D integrated chip includes a logic layer, a memory computing layer, and a reconfigurable layer stacked sequentially, with interconnections between these layers. The logic layer transmits computation signals and data to the memory computing layer and configuration data and signals to the reconfigurable layer. The memory computing layer, under the control of the computation signals, performs matrix multiplication or addition on the computation data and outputs the computation results. The reconfigurable layer, under the control of the configuration signals, performs reconfigurable processing on the computation results according to the configuration data. This application endows the chip with flexible programmability and reconfigurability.
Owner:SEMICON TECH INNOVATION CENT(BEIJING) CORP +1