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296results about How to "Width minimized" patented technology

Reclosable package and method

InactiveUS6070723AWidth minimizedMaximizing usable package volumePackaging vehiclesContainers for machinesEngineeringBlisters
A reclosable package and method having an integral reclosable door adjacent one end that permits article removal from the end of the package. The package is comprised of a thermoformed blister body joined to a thermoformed backing body. The blister body has sidewalls, endwalls and a peripheral flange broken into a first section adjacent the door where the height of the sidewalls decrease and a second section opposite the door with the first section angled relative to the second section. The backing body carries the door and has an integral peripheral rib inboard of a peripheral flange with the flange having a first section about the door and a second section disposed away from the door. The rib has a pair of longitudinally-extending sections divided by a notch that preferably is a transverse rib that causes the door to bend about a desired fold line that runs generally through or adjacent the ribs or notches when urged away from a closed position. In a preferred method, after performing a multilevel trim operation to trim the multiplanar flanges of one or both the blister body and the backing body, the two bodies are joined at the flange sections about a portion of the periphery to adjacent the fold line using an energy welding process, preferably RF welding, that produces a narrow tear seam that enables finished package flange width to be minimized to thereby also minimize package width.
Owner:PORTAGE PLASTICS

Semiconductor device structure and methods of making

A process for fabricating a semiconductor device having reduced capacitance for high frequency circuit protection is disclosed that comprises first forming an n+ buried layer in a p-type substrate by depositing n-type dopant on the top surface of the substrate and then drive in or by implanting n-type material into the substrate, and then growing an n-type epitaxial layer atop the n+ buried layer as the device layer. Trenches that surrounds the device region with depth extending from the top surface, going through the n+ buried layer and reaching down to the substrate are then formed and then an n+ layer on the sidewalls of the trenches is formed by diffusion or ion implantation. The trenches are then filled by growing a layer of thermal oxide on the sidewalls of the trenches and followed by deposition of plasma enhanced oxide, nitride, TEOS oxide CVD oxide, or polysilicon into the trenches and then planarizing the top surface by plasma etch back or polishing. Then n+ region of the device is formed by forming an oxide layer on the top surface of the device layer and then etching the oxide by photolithography, then depositing n-type dopant material and then driving in by high temperature diffusion. Finally p+ region of the device is formed by etching the oxide using photolithography, then depositing p-type dopant material by solid or gas phase deposition or ion implantation and then driving in by high temperature diffusion so that the breakdown voltage between cathode and anode of the device is set to a targeted voltage for high frequency circuit protection.
Owner:HU JERRY +2
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