There is provided a
phase locked loop (PLL) having an improved phase unlock detection function. The PLL generates a
clock pulse
signal at a frequency from a
synchronization signal of a
cathode ray tube (CRT) monitor. The PLL includes a
phase frequency detector (PFD), a
charge pump, a
loop filter, a
Voltage Controlled Oscillator (VCO), a divider, a phase unlock detection circuit, a phase lock / unlock detection circuit, and an output circuit. The PFD compares a phase and frequency of a
synchronization signal to that of a reference
signal, and outputs an up or down
signal. The
charge pump outputs a pumping current in response to the up or down signal. The
loop filter outputs a control
voltage according to the pumping current. The VCO outputs a
clock pulse signal having a frequency determined by a control
voltage. The divider divides the
clock pulse signal by a division ratio and outputs a reference signal. The phase unlock detection circuit detects an initial generation of a phase unlock from the up or down signal, outputs a first detection signal, and outputs an internal
control signal according to the up or down signal. The phase lock / unlock detection circuit outputs a second detection signal, in response to the internal
control signal and the first detection signal. The output circuit performs a logic operation on the first detection signal and the second detection signal and outputs a third detection signal. Therefore, the PLL having the improved phase lock / unlock detection function can improve
system stability in
mode switching of a
CRT monitor, by quickly detecting an initial generation of phase unlock without a time
delay.