Disclosed is a
display device including display unit, a column driver, a
delay control circuit, an output switch
control circuit, and a display controller. The display unit includes a plurality of pixel electrodes arranged at intersections between a plurality of
data lines and a plurality of scan lines in a
matrix form and TFTs. One of a drain and a source of each of the TFTs is connected to a corresponding one of the pixel electrodes. The other one of the drain and the source of each of the TFTs is connected to a corresponding one of the
data lines, and a gate of each of the TFTs is connected to a corresponding one of the scan lines. The scan driver supplies a scan
signal to each of the
scan line in a preset scan cycle. The column driver includes D / A converter circuits for converting video data to gray scale signals, a plurality of buffer amplifiers for sequentially amplifying and outputting the gray scale signals in a preset output cycle, and an output switch circuit including a plurality of switches connected to output terminals of the buffer amplifiers and the
data lines, respectively. The
delay control circuit controls the scan driver so that the preset scan cycle is delayed from the preset output cycle just by a preset
delay time. The output switch control circuit controls the output switch circuit to be kept off during the preset
delay time. The display controller controls the video data, scan driver, column driver, delay control circuit, and output switch control circuit, respectively.