60results about How to "Reduce stall" patented technology

The present invention relates to a method and system for performing a data transfer between a shared memory (16) of a processor device (10) and a circuitry (20) connected to the processor device (10), wherein the data transfer is performed by triggering a DMA transfer of the data to the processor device, adding the DMA transfer to a transaction log, and providing the transaction log to the processor device, when the transaction log has reached a predetermined depth limit. The processor device is then informed of the DMA transfer of the transaction log, so as to be able to validate the transferred data. Thereby, significant background data movement can be provided without introducing high core overheads at the processor device (10).

A pipelined processor includes a branch acceleration technique which is based on an improved branch cache. The improved branch cache minimizes or eliminates delays caused by branch instructions, especially data-dependent unpredictable branches. In pipelined and multiply pipelined machines, branches can potentially cause the pipeline to stall because the branch alters the instruction flow, leaving the prefetch buffer and first pipeline stages with discarded instructions. This has the effect of reducing system performance by making the branch instruction appear to require multiple cycles to execute. The improved branch cache differs from conventional branch caches. In particular, the improved cache is not used for branch prediction, but rather, the improved branch cache avoids stalls by providing data that will be inserted into the pipeline stages that would otherwise have stalled when a branch is taken. Special architectural features and control structures are supplied to minimize the amount of information that must be cached by recognizing that only selected types of branches should be cached and by making use of available cycles that would otherwise be wasted. The improved branch cache supplies the missing information to the pipeline in the place of the discarded instructions, completely eliminating the pipeline stall. This technique accelerates performance, especially in real-time code that must evaluate data-dependent conditions and branch accordingly.

A method for controlling a vehicle engine having a plurality of cylinders is provided. The method comprises: during engine idling, advancing spark timing of at least one cylinder to before a peak torque timing, and retarding spark timing from the advanced timing toward the peak torque timing in response to decreased engine speed to maintain idling speed.

A method for controlling a vehicle engine having a plurality of cylinders is provided. The method comprises: during engine idling, advancing spark timing of at least one cylinder to before a peak torque timing, and retarding spark timing from the advanced timing toward the peak torque timing in response to decreased engine speed to maintain idling speed.