Patents
Literature
Hiro is an intelligent assistant for R&D personnel, combined with Patent DNA, to facilitate innovative research.
Hiro

35results about How to "Excellent moisture resistance reliability" patented technology

Ceramic electronic component

A ceramic electronic component includes a body including a dielectric layer and first and second internal electrodes, a first external electrode including a first electrode layer electrically connected to the first internal electrode, a first inorganic insulating layer disposed on the first electrode layer, and a first plating layer disposed on the first inorganic insulating layer, a second external electrode including a second electrode layer electrically connected to the second internal electrode, a second inorganic insulating layer disposed on the second electrode layer, and a second plating layer disposed on the second inorganic insulating layer, and a third inorganic insulating layer disposed on the body and connected to the first and second inorganic insulating layers. The first, second and third inorganic insulating layers comprise one or more of SiO2, Al2O3 and ZrO2, and the first, second and third inorganic insulating layers have a thickness within a range from 20 nm to 150 nm.
Owner:SAMSUNG ELECTRO MECHANICS CO LTD

Process for producing semiconductor devices, and semiconductor device

InactiveCN105377980AImprove heat resistanceExcellent resistance to temperature cyclingEpoxySemiconductor chip
A process for semiconductor device production which comprises: a preparation step in which a substrate for element mounting (108) equipped with a plurality of package areas (114) separated by dicing regions (112) is prepared; a mounting step in which semiconductor chips (116) are mounted respectively on the package areas (114) of the substrate for element mounting (108); a molding step in which the semiconductor chips (116) are simultaneously encapsulated by molding with an encapsulating epoxy resin composition; and a chip formation step in which the resultant structure is diced along the dicing regions (112) to separate the individual encapsulated semiconductor chips (116). The encapsulating epoxy resin composition comprises (A) an epoxy resin, (B) a hardener, (C) a silicone resin, (D) an inorganic filler, and (E) a hardening accelerator, wherein the silicone resin (C) is a branched silicone resin that is a methylphenyl-type thermoplastic silicone resin and has repeating structural units represented by general formulae (a), (b), (c), and (d). (In the formulae, symbol * indicates a bond with the Si atom contained in a repeating structural unit of another or the same kind; and R1a, R1b, R1c, and R1d are each a methyl or phenyl group and may be the same as or different from one another. The content of Si-bonded phenyl groups is 50 mass% or higher of the molecule, and the content of Si-bonded OH groups is less than 0.5 mass% of the molecule.) The formulae is shown in the specification.
Owner:SUMITOMO BAKELITE CO LTD

Multilayer ceramic capacitor and method of manufacturing the same

ActiveUS20190019624A1Increase in volume ratioExcellent moisture tolerance reliabilityFixed capacitor electrodesFixed capacitor dielectricMetallurgyDielectric layer
A multilayer ceramic capacitor includes a body having a dielectric layer and internal electrodes disposed to be alternately exposed to the third and fourth surfaces with the dielectric layer interposed therebetween. External electrodes include connection parts respectively formed on opposing surfaces of the body, band parts formed to extend from the connection parts to portions of side surfaces of the body, and corner parts in which the connection parts and the band parts are contiguous. A thickness of each of the external electrodes may be 50 nm to 2 μm. The external electrodes may be formed using a barrel-type sputtering method. A ratio t2 / t1 may satisfy 0.7 to 1.2, where t1 is a thickness of each connection part and t2 is a thickness of each band part. A ratio t3 / t1 may satisfy 0.7 to 1.0, where t3 is a thickness of each corner part.
Owner:SAMSUNG ELECTRO MECHANICS CO LTD

Adhesive film for semiconductor, composite sheet, and method for producing semiconductor chip using them

There is provided an adhesive film for a semiconductor, which can be attached to a semiconductor wafer at low temperature and which allows semiconductor chips to be obtained at high yield from the semiconductor wafer while sufficiently inhibiting generation of chip cracks and burrs. The adhesive film for a semiconductor comprises a polyimide resin that can be obtained by reaction between a tetracarboxylic dianhydride containing 4,4'-oxydiphthalic dianhydride represented by chemical formula (I) below and a diamine containing a siloxanediamine represented by the following general formula (II) below, and that can be attached to a semiconductor wafer at 100 DEG C or below.
Owner:HITACHI CHEM CO LTD

Organic el device and production method therefor

This organic EL device (100) has a substrate (1), a drive circuit layer (2), a first inorganic protective layer (2Pa), an organic planarizing layer (2Pb), an organic EL element layer (3), a second inorganic protective layer (2Pa2), and a TFE structure (10). The TFE structure has a first inorganic barrier layer (12), an organic barrier layer (14), and a second inorganic barrier layer (16). When viewed from a normal line of the substrate, the organic planarizing layer is formed within a region where the first inorganic protective layer is formed, while an organic EL element is disposed within aregion where the organic planarizing layer is formed. The TFE structure has an exterior edge which intersects with a lead-out line (32) and which is situated between an exterior edge of the organic planarizing layer and an exterior edge of the first inorganic protective layer. In a portion where the first inorganic protective layer and the first inorganic barrier layer are in direct contact with each other on the lead-out line, the first inorganic barrier layer has, in a cross-section parallel to the line width direction of the lead-out line, a lateral face that is configured to have a taper angle theta (12) of less than 90 DEG. The organic planarizing layer has a surface which exceeds 50 nm in arithmetic average roughness Ra, while the second inorganic protective layer has a surface thatis not more than 50 nm in arithmetic average roughness Ra.
Owner:SAKAI DISPLAY PROD

Organic el device and production method therefor

An organic EL device (100A) comprises a peripheral region (R2) and an active region (R1) containing a plurality of organic EL elements (3), and includes an element substrate (20) having a plurality oforganic EL elements, and a thin film seal structure (10A) covering the plurality of organic EL elements. The thin film seal structure comprises a first inorganic barrier layer (12), an organic barrier layer (14) in contact with the upper surface of the first inorganic barrier layer, and a second inorganic barrier layer (16) in contact with the upper surface of the first inorganic barrier layer and the upper surface of the organic barrier layer. The peripheral region comprises a first protruding structure (22a) containing a section extending along at least one edge of the active region, and anextending section (12e) of the first inorganic barrier layer extending over the first protruding structure. The first protruding structure includes a first part and second part. The first part is closer to the top portion of the first protruding structure than the second part and, as observed from the normal direction to the base board, a cross section parallel to the substrate surface of the first part includes a part that does not overlap with the cross section parallel to the substrate surface of the second part.
Owner:SAKAI DISPLAY PROD
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products