7results about How to "Reduce packaging steps" patented technology

The invention discloses a carrier tape production line and a production method, and belongs to the field of carrier tapes. The carrier tape production line comprises a composite extruder, an automatic adjusting type carrier tape forming machine, processing equipment and a winding machine; the automatic adjusting type carrier tape forming machine comprises a first position automatic adjusting assembly, a first machine table, a forming roller assembly, a roller type flattening assembly, a second position automatic adjusting assembly, a hot air gun, a guide wheel, a controller and a display screen, and the first machine table is arranged at the adjusting end of the first position automatic adjusting assembly; the hot air gun is arranged at the adjusting end of the second position automatic adjusting assembly, the roller type flattening assembly comprises a fixed roller set and an adjustable roller set which are oppositely arranged, and the adjustable roller set is provided with a third position automatic adjusting assembly. The first position automatic adjusting assembly, the forming roller assembly, the roller type flattening assembly, the second position automatic adjusting assembly and the hot air gun are all electrically connected with the controller, and the controller is electrically connected with the display screen. The overall carrier tape production efficiency and the product quality are high.

The utility model discloses a forestry nursery stock transplanting device for forest farms in the technical field of nursery stock transplanting, which comprises a bottom plate, a lifting component and a seedling digging component, the lifting component is mounted on the bottom plate, the seedling digging component is mounted on the lifting component, a first speed regulating box is mounted on the bottom plate, and the lifting component is in transmission connection with the first speed regulating box. A first threaded rod is rotationally connected to the first speed regulation box, a material receiving plate is in threaded connection to the first threaded rod, a packaging disc is movably connected to the material receiving plate, a material pushing mechanism is arranged on the bottom plate and movably connected with the packaging disc, a rotating column is in transmission connection to the lifting assembly, a half gear is installed on the rotating column, and a second speed regulation box is installed on the bottom plate. A one-way wheel is mounted on the second speed regulation box, the one-way wheel is in meshed connection with a half gear, and the pushing mechanism is in transmission connection with the second speed regulation box, so that the seedling digging efficiency of the equipment is further improved, the equipment is more convenient during seedling digging, and the steps of transferring and packaging are reduced.

This invention provides a glass substrate optoelectronic co-packaging structure and its fabrication method, addressing the technical problems of existing glass substrate-based optoelectronic co-packaging structures, such as easy mounting errors during assembly, poor structural stability, and easy displacement relative to the glass substrate during operation, resulting in transmission loss. The glass substrate optoelectronic co-packaging structure of this invention innovatively embeds optoelectronic integrated chips and integrated circuit chips within the glass substrate, and also incorporates a microbridge structure and a pluggable fiber array within the glass substrate. This not only reduces the overall volume of the packaging structure but also effectively improves the structural stability of each component, reducing failures caused by poor packaging or component detachment, and increasing packaging yield. More importantly, this design effectively ensures alignment accuracy, enabling precise docking between the optoelectronic integrated chip and the external optical signal array, achieving efficient and low-loss transmission of optical signals.

The invention relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging structure and packaging method.The semiconductor packaging structure comprises a plurality of packaging frames, first base islands and second base islands, the first base islands and the second base islands are connected in the packaging frames, separation gaps are formed between the first base islands and the second base islands, first chips are arranged on the first base islands, and second chips are arranged on the second base islands; the first base island is provided with a first chip, the second base island is provided with a second chip, the first base island is integrally connected with a first pin, a third connection point of the first chip is connected with the first base island through a wire, a first connection point of the first chip is connected with a second pin through a wire, a second connection point of the first chip is connected with the second base island through a wire, and a fourth connection point of the second chip is connected with the first base island through a wire. A fifth connecting point of the second chip is connected with a third pin through a wire, the third pin is fixedly connected to the packaging frame, the second pin is fixedly connected with the first pin or the third pin or the packaging frame, and the first chip and the second chip are separated through the separation gap, so that the first chip and the second chip do not interfere with each other.

The embodiment of the invention relates to a packaging structure and a preparation method thereof. The packaging structure comprises a packaging substrate; a buffer chip located on the package substrate; the chip structure comprises a first chip and a second chip which are symmetrically arranged on the buffer chip; the packaging layer covers the chip structure, the buffer chip and the packaging substrate. According to the packaging structure and the preparation method thereof provided by the embodiment of the invention, the first chip and the second chip are symmetrically arranged on the buffer chip, and then the chip structure, the buffer chip and the packaging layer of the packaging substrate are formed, so that the packaging structure is formed. Therefore, the chip structure and the buffer chip do not need to be packaged independently, the packaging steps are saved, and the packaging efficiency is improved.

The invention discloses a password calculation method and device, equipment and a medium, and relates to the technical field of information security, and the method comprises the steps: a first password calculation service integrated in a preset gateway in advance determines target processing performance required by a transaction request; if the target processing performance belongs to the first preset category processing performance, asynchronously calling a password device locally to carry out password calculation on the transaction request; if the target processing performance is a second preset type processing performance, sending the transaction request to a second password calculation service so as to call a password device to carry out password calculation on the transaction request; the first preset category processing performance is higher than the second preset category processing performance; the processing performance of the first cryptographic computing service is higher than that of the second cryptographic computing service, and the resource occupation of the first cryptographic computing service is smaller than that of the second cryptographic computing service. Through differentiated password calculation, the request processing rate can be improved, and resource consumption can be reduced.

The utility model discloses a kind of packaging structures, applied to semiconductor technical field, comprising: photoelectric sensing chip and glass substrate;The upper surface of photoelectric sensing chip is provided with photosensitive area, and at least two first pads around photosensitive area;First pad surface is provided with conductive bump;Glass substrate is set on the upper surface of photoelectric sensing chip;Glass substrate lower surface is provided with rewiring layer;Rewiring layer includes at least two second pads around photosensitive area;And glass substrate is also provided with solder ball electric contact with second pad;Photoelectric sensing chip is electrically connected by conductive bump, second pad and solder ball.The utility model packaging thickness is small, heat dissipation performance is good, reliability is high, and cost is low.