32results about How to "Less circuitry" patented technology

A light-sensitive (i.e., touch-sensitive) display device that requires less circuitry than the currently available light-sensitive display devices is presented. Unlike the currently available devices, which require at least two switching elements and a capacitor to implement a photosensitive switch, the invention only requires one switching element. The device of the invention includes a substrate with a plurality of scan lines, a plurality of read-out lines, a power line, and an array of photosensitive switches formed thereon. The scan lines and the read-out lines extend in directions that are substantially perpendicular to each other, forming pixels. One photosensitive switch is formed in each pixel, and each photosensitive switch has one light-sensitive transistor. The transistor connects the power line to one of the read-out lines in response to sensing incident light.

A cache memory circuit is provided for use in a data processing apparatus. The cache has a memory array and circuitry for receiving both a transaction input signal and a priority input signal. The priority input signal provides priority information with regard to one or more of the cache transactions received in the transaction input signal. A cache controller is provided for servicing the cache transactions. The cache controller is responsive to the priority input signal to control servicing for at least one of the cache transactions in dependence upon the priority information.

A distributed control system has a plurality of distributed field devices, each of which contains a transducer and a wireless transceiver. The distributed control system includes a base station transceiver, a database and a virtual transmitter application in communication with the database. Each field device transmits and receives data via wireless signals between the communications boards and the base station. The data is stored in the database for later retrieval and evaluation by the virtual transmitter application. The deployed field device senses information and transmits the sensed information wirelessly to a base station. The sensed information is stored in memory on a computer system, and programmatically groomed to provide a measurement value, upon request by a user.

Method and apparatus for block boundary detection is described. A signal is received. The signal is quantized to provide a quantized signal to at least one correlator, the quantized signal being a sequence of samples. The sequence of samples and a reference template including totaling partial results from the at least one correlator are cross-correlated to provide a result, the result being a symbol timing synchronization responsive to the cross-correlation also known as block boundary detection. The cross-correlation is provided in part by combining by exclusive-ORing a regression vector obtained from the sequence of samples and a coefficient term vector obtained from the reference template.

A system for compensating and driving a loudspeaker includes an open loop loudspeaker controller that receives and processes an audio input signal and provides an audio output signal. A dynamic model of the loudspeaker receives the audio output signal, and models the behavior of the loudspeaker and provides predictive loudspeaker behavior data indicative thereof. The open loop loudspeaker controller receives the predictive loudspeaker behavior data and the audio input signal, and provides the audio output signal as a function of the audio input signal and the predictive loudspeaker behavior data.

A memory device with a data path circuit having support in the sense-amp region for compression testing of the device. The data path circuit uses NOR logic compression to provide a scalable design which may be extended to large circuits.

Abstract of the Disclosure

The invention relates to a power supply device having several switch-mode power supplies connected in parallel to supply at least one consuming unit, each switch-mode power supply generating an output current I0 and an output voltage U₀(I₀, R_L) that is a function of the output current I₀ and a load resistance R_L, and having a control device for each switch-mode power supply, the control device having a first stage with a P element (54) that receives a P element input voltage which is derived from the output voltage U₀(I₀, R_L), and generates a P element control voltage U_VS, that is used to control the respective switch-mode power supply, the first stage being active when 0 ≤ I₀≤ I_0P, a second stage having a current reproduction circuit which reproduces the output current I₀ of the respective switch-mode power supply and generates an output current control voltage U_P which is used to control the respective switch-mode power supply, the second stage being active when I_0P≤ I₀≤ I_0S, and a third stage having an amplifier circuit which amplifies a signal proportional to the output current I₀ and generates an amplified output current control voltage m·U_S which is used to control the respective switch-mode power supply, the third stage being active when I_0S≤ I₀≤ I_K.

An apparatus having a memory and a circuit is disclosed. The memory may be configured to store a picture being encoded. The circuit may be configured to calculate a plurality of first arrays directly from a plurality of neighboring samples around a current block of the picture. Each first array generally represents a respective one of a plurality of intra-prediction modes. Each first array may be spatially smaller than the current block. The circuit may also be configured to calculate a second array from a plurality of current samples in the current block. The second array may spatially match the first arrays. The circuit may be further configured to generate a plurality of scores of the intra-prediction modes by comparing the first arrays with the second array and select a given one of the intra-prediction modes corresponding to a lowest of the scores to encode the current block.

Pixel circuits, capable of operating in either “snapshot” or “rolling integration” mode, and compatible with a conformal photodiode coating. Preferred embodiments of the present invention are compatible with these coating materials, as well as others, including amorphous Silicon. The preferred pixel circuits includes additional transistors not provided in prior art pixel circuits to divert leakage current away from integration nodes when not integrating, to reset the integration node, and to buffer and select the integrated voltage.

The invention relates to a user interface device for controlling an electrical consumer, in particular, a light system (545). Further, it relates to light system using such user interface device. To provide a user interface device for controlling a light system (545), which could be easily operated and provides the possibility to recognize a selected preset in all areas of the display device (112), a user interface device for controlling a consumer load (545) is proposed, comprising: an input device (111); and a display device (112), wherein the input device (111) and the display device (112) are arranged interested to each other in one common layer or in two layers respectively stacked on each other. The display device (112) is adapted to display at least a first colored scale (210) indicating a first range of values adjustable by an user input on the first colored scale (210) and to display a first feedback indicator (215) within the first colored scale (210) indicating the current value of the first range of values output by the user interface device to a consumer load (545).

Digital-to-analog converter (DAC) circuits employing resistor rotator circuits configured to be included in analog-to-digital converter (ADC) circuits are disclosed. In one aspect, a DAC circuit includes multiple DAC stages, each of which may be configured to generate one or more DAC analog signals corresponding to selected resistances within the DAC stage. Each DAC stage is configured to receive a corresponding top and bottom voltage. Each DAC stage is configured to generate a number of DAC analog signals based on the corresponding top voltage and the corresponding bottom voltage, as well as on the selected resistance of the DAC stage. Each DAC stage includes an adjusting circuit comprising a resistance configured to adjust a resistance of the corresponding DAC stage such that a parallel combination of the resistance of the adjusting circuit and a resistance of a next DAC stage is maintained at an ideal resistance level.

A method of performing a scaled sum-of-product operation in a processor in response to multiply-and-accumulate (MAC) instructions. The method includes accessing a first number, accessing a second number, and accessing a shift value. The first number is multiplied by the second number, the resulting product comprising a third number that includes a most significant portion and a least significant portion. The method includes executing a first MAC instruction, executing a second MAC instruction, and storing a final result of the scaled sum-of-product operation. Executing the first MAC instruction comprises right-shifting the least significant portion of the third number according to the shift value; accessing a least significant portion of a fourth number; and adding the right-shifted least significant portion of the third number to the least significant portion of the fourth number, the resulting sum comprising a least significant portion of the final result of the scaled sum-of-product operation.