14 results about "Semiconductor waveguides" patented technology

A semiconductor optical device includes n-doped, p-doped, and active layers, an optical waveguide structure, and drive current structure(s). The waveguide structure defines optical mode(s); the drive current structure defines a drive current path. One or both of those structures are arranged to result in a selected (or maximized) degree of overlap between lateral profiles of current density and optical intensity. The optical device can be arranged as a diode laser or optical amplifier.

An integrated chip including a semiconductor waveguide layer. A core portion of the semiconductor waveguide layer protrudes upward from a base portion of the semiconductor waveguide layer. A first heat radiator is spaced over the semiconductor waveguide layer and laterally spaced from the core portion in a first direction. A second heat radiator is spaced over the semiconductor waveguide layer and laterally spaced from the core portion in a second direction. A first dielectric layer is between the first heat radiator and the semiconductor waveguide layer and between the second heat radiator and the semiconductor waveguide layer. A distance between the first heat radiator and the semiconductor waveguide layer is less than a distance between the first heat radiator and the core portion. A distance between the second heat radiator and the semiconductor waveguide layer is less than a distance between the second heat radiator and the core portion.

The invention provides a grating-integrated semiconductor light-emitting structure and a preparation method thereof, the grating-integrated semiconductor light-emitting structure comprises a semiconductor substrate layer, a gain structure and a grating waveguide dielectric structure, and the junction of the grating waveguide dielectric structure and the gain structure is provided with an anti-reflection structure; the gain structure is located on one side of a part of the semiconductor substrate layer in the fast axis direction, and the gain structure comprises a first semiconductor limiting layer, a first semiconductor waveguide layer, an active layer, a second semiconductor waveguide layer and a second semiconductor limiting layer which are sequentially arranged in the fast axis direction; the grating waveguide dielectric structure is located on one side of a part of the semiconductor substrate layer in the fast axis direction and located on one side of the gain structure in the cavity length direction, and a grating is integrated in the grating waveguide dielectric structure. And the wavelength temperature drift coefficient of the semiconductor light-emitting structure of the integrated grating is reduced.

The embodiment of the utility model provides an integrated crystal grain. An integrated die includes a substrate, a semiconductor waveguide layer, a conductive heater wire, a first heater contact, and a second heater contact. The semiconductor waveguide layer is over the substrate. A base portion of the semiconductor waveguide layer extends across over the substrate. The ridge portion of the semiconductor waveguide layer protrudes upward beyond the base portion. Conductive heater lines are spaced over the ridge portion of the semiconductor waveguide layer. First and second heater contacts extend from the conductive heater wire to a base portion of the semiconductor waveguide layer on opposite sides of the ridge portion of the semiconductor waveguide layer.

An integrated chip including a base dielectric layer and a multi-tiered semiconductor waveguide layer over the base dielectric layer. The multi-tiered semiconductor waveguide layer has a first waveguide tier having a first width at a first height over the base dielectric layer. The multi-tiered semiconductor waveguide layer has a second waveguide tier having a second width, greater than the first width, at a second height, less than the first height, over the base dielectric layer. A cladding layer is over the multi-tiered semiconductor waveguide layer. A multi-tiered conductive heater layer is over the cladding layer. The multi-tiered conductive heater layer has a first heater tier over the first waveguide tier. The multi-tiered conductive heater layer has a pair of second heater tiers at the first height, over the second waveguide tier, and on opposite sides of the first waveguide tier.

The method includes: performing a first etch on a substrate, where the substrate includes six cross sections arranged in sequence to define five partitions along a first direction, where the first etch forms a first protruding region extending from first to fifth partitions and two first connection regions on both sides of the first protruding region; performing second etching on the two first connection areas to form a strip waveguide along the sixth cross section; performing third etching on the two first connection areas to form a rib waveguide along a third cross section; and performing fourth etching on the two first connection regions to form the deep-rib waveguide along the first cross section. The embodiment of the invention also relates to a semiconductor waveguide device and a forming method thereof.

A silicon-based hybrid integrated laser and chip, the silicon-based hybrid integrated laser comprising: a silicon substrate, an oxidation buried layer, a silicon optical waveguide, a dielectric layer, a III-V semiconductor waveguide, a plurality of metal electrodes, and one or more heat dissipation structures; along a first direction, the silicon substrate, the oxidation buried layer, the silicon optical waveguide, the dielectric layer, and the III-V semiconductor waveguide are stacked; the III-V semiconductor waveguide comprises an N-type semiconductor, a multiple quantum well active layer, and a P-type semiconductor stacked along the first direction, and the N-type semiconductor is in conductive connection with the metal electrode; the heat dissipation structure is accommodated in the oxidation buried layer and the dielectric layer, one end of the heat dissipation structure along the first direction is in thermal connection with the metal electrode, and the other end of the heat dissipation structure along the first direction is in thermal connection with the silicon substrate. The silicon-based hybrid integrated laser and chip provided by the embodiments of the present application can improve the heat dissipation and communication performance of the chip in which the silicon-based hybrid integrated laser is located.

The invention relates to an optoelectronic component (1) suitable for integration into an optoelectronic circuit, the component (1) comprising: - a III-V semiconductor membrane comprising: • a P-doped layer (2) called P layer; • an intrinsic layer (3) deposited on the P layer (2); and • an N-doped layer called N layer deposited on the intrinsic layer (3); - an asymmetric photonic-crystal waveguide (6, 16, 26) called PhC waveguide formed in the membrane by a two-dimensional photonic crystal on one longitudinal side and by a total internal reflection face on the other longitudinal side; - electrical contacts (10, 11) arranged respectively on either side of the PhC waveguide (6, 16, 26) in the plane of the membrane, suitable for injecting charge carriers laterally relative to the membrane into the PhC waveguide (6, 16, 26); the layers (2, 3, 4) being arranged so that the intrinsic layer and the N layer (3, 4) only partially cover the P layer (2), forming a lateral face (5) extending perpendicularly from the surface of the P layer (2), part of the lateral face (5) forming the total internal reflection face of the PhC waveguide; the PhC waveguide (6, 16, 26) being arranged to be evanescently coupled to a passive semiconductor waveguide (12) in at least one coupling region.

A semiconductor photonic device includes a semiconductor waveguide, a cladding structure surrounding the semiconductor waveguide, and an optical isolation structure disposed in the cladding structure. A top surface of the optical isolation structure is lower than a top surface of the semiconductor waveguide, and a bottom surface of the optical isolation structure is higher than a bottom surface of the semiconductor waveguide.

A method for fabricating a sensor comprises: (a) providing a wafer comprising a substrate, a dielectric layer on the substrate, and a semiconductor adlayer on the dielectric layer; (b) enacting microlithographic processing on the semiconductor adlayer to define: (i) a curved and elongate semiconductor waveguide confined to the dielectric layer, (ii) an in-coupling window arranged at a first end of the waveguide and configured to couple optically to an optical source, and (iii) an out-coupling window arranged at a second end of the waveguide and configured to couple optically to an optical detector; and (c) selectively etching the dielectric layer to define: (iv) a first dielectric region that supports and encloses the first end of the waveguide; (v) a second dielectric region that supports and encloses the second end of the waveguide; and (vi) a third dielectric region that supports but does not enclose a middle segment of the waveguide.

This invention relates to a semiconductor waveguide-SPP waveguide coupler, belonging to the field of integrated nanophotonic chip technology. It includes a first coupler and a second coupler. The first coupler comprises a first semiconductor waveguide, a first SPP waveguide, and a second SPP waveguide; the second coupler comprises a second semiconductor waveguide, a third SPP waveguide, and a fourth SPP waveguide. The first semiconductor waveguide is located between the first and second SPP waveguides, and forms a V-shaped tip structure to achieve the conversion from optical wave mode to SPP mode. The second semiconductor waveguide is located between the third and fourth SPP waveguides, and has a V-shaped groove at its input end to achieve the conversion from SPP mode to optical wave mode. This invention can convert optical waves in a semiconductor to SPP mode in a metal waveguide, and can also transmit SPP mode from a metal waveguide to optical wave mode in a semiconductor waveguide.

A method includes performing a first etch on a substrate, wherein the substrate includes six cross sections arranged in sequence to define five zones along a first direction, wherein the first etch forms a first protrusion region extending from the first to fifth zones and two first connecting regions on two sides of the first protrusion region; performing a second etch on the two first connecting regions to form a strip waveguide along the sixth cross section; performing a third etch on the two first connecting regions to form a rib waveguide along the third cross section; and performing a fourth etch on the two first connecting regions to form a deep-rib waveguide along the first cross section.

The application provides an integrated grating semiconductor light-emitting structure and a preparation method thereof. The integrated grating semiconductor light-emitting structure comprises a semiconductor substrate layer, a gain structure and a grating waveguide medium structure, and the junction of the grating waveguide medium structure and the gain structure has an anti-reflection structure. The gain structure is located on one side of the semiconductor substrate layer along a fast axis direction, and the gain structure comprises a first semiconductor confinement layer, a first semiconductor waveguide layer, an active layer, a second semiconductor waveguide layer and a second semiconductor confinement layer arranged in sequence along the fast axis direction. The grating waveguide medium structure is located on one side of the semiconductor substrate layer along the fast axis direction and on one side of the gain structure along a cavity length direction, and the grating waveguide medium structure is integrated with a grating. The wavelength temperature drift coefficient of the integrated grating semiconductor light-emitting structure is reduced.

A semiconductor optical device includes n-doped, p-doped, and active layers, an optical waveguide structure, and drive current structure(s). The waveguide structure defines optical mode(s); the drive current structure defines a drive current path. One or both of those structures are arranged to result in a selected (or maximized) degree of overlap between lateral profiles of current density and optical intensity. The optical device can be arranged as a diode laser or optical amplifier.