31 results about "Threshold voltage degradation" patented technology

It is an object of the present invention to provide a device which can be easily manufactured and obtain a ground state of an arbitrary Ising model. A semiconductor device includes a first memory cell and a second memory cell that interacts with the first memory cell, in which storage content of the first memory cell and the second memory cell is stochastically inverted. The storage content is stochastically inverted by dropping threshold voltages of the first memory cell and the second memory cell. The threshold voltages of the first and second memory cells are dropping by controlling substrate biases, power voltages, or trip points of the first and second memory cells.

A GaN power switching device comprises a GaN transistor switch SW_MAIN has an integrated drain voltage sense circuit, which comprises GaN sense transistor SW_SEN and GaN sense resistor RSEN, which at turn-on form a resistive divider for sensing the drain voltage of SW_MAIN to provide a drain voltage sense output VDSEN. Fault detection logic circuitry of a driver circuit generates a fault signal FLT when VDSEN reaches or exceeds a reference voltage Vref, which triggers fast turn-off of the gate of SW_MAIN, e.g. within less than 100 ns of an overcurrent or short circuit condition. During turn-off, RSEN resets VDSEN to zero. For two stage turn-off, the driver circuit further comprises fast soft turn-off circuitry which is triggered first by the fault signal to pull-down the gate voltage to the threshold voltage, followed by a delay before full turn-off of the gate of SW_MAIN by the gate driver.

The invention relates to the technical field of integrated circuits and provides a threshold voltage degradation measuring circuit. The circuit comprises two MOS (Metal Oxide Semiconductor) tubes which are connected in series, wherein the first MOS tube is a detected tube; a grid electrode of the first MOS tube is connected with first direct-current voltage, a source electrode and a substrate of the first MOS tube are simultaneously connected with source electrode voltage, and a drain electrode of the first MOS tube is connected with an output end; a grid electrode and a drain electrode of the second MOS tube are simultaneously connected with second direct-current voltage, and a source electrode and a substrate of the second MOS tube are simultaneously connected with the output end. According to the scheme disclosed by the invention, the threshold voltage degradation measuring circuit with a simple structure is provided; the circuit only comprises the two MOS tubes which are connected in series and the threshold voltage degradation condition of the tube to be detected can be directly measured by only measuring the voltage change of the output end; and the circuit only relates to the obtaining of one physical amount and does not need to carry out secondary process and analysis, so that the technical scheme has the advantages of simple structure, convenience for operation, time-saving property, accurate and direct results and easiness in implementation.

Methods and systems for computing threshold voltage degradation of transistors in an array of memory cells are disclosed. In accordance with one method, a process that models an expected usage of the array is selected. In addition, a hardware processor can run the process to populate the array with data over time to simulate the expected usage of the array. The method further includes compiling data that detail different durations at which each of the memory cells in the array stores 1 or at which each of the memory cells in the array stores 0. For each separate grouping of memory cells that share a common duration of the different compiled durations, a threshold voltage degradation is determined for each transistor in the corresponding grouping of cells based on at least one biased temperature instability model.