31 results about "Threshold voltage degradation" patented technology

It is an object of the present invention to provide a device which can be easily manufactured and obtain a ground state of an arbitrary Ising model. A semiconductor device includes a first memory cell and a second memory cell that interacts with the first memory cell, in which storage content of the first memory cell and the second memory cell is stochastically inverted. The storage content is stochastically inverted by dropping threshold voltages of the first memory cell and the second memory cell. The threshold voltages of the first and second memory cells are dropping by controlling substrate biases, power voltages, or trip points of the first and second memory cells.

The invention provides bias voltage temperature instability detection circuit and detection method. The bias voltage temperature instability detection circuit comprises an odd number of fundamental oscillation units. Each fundamental oscillation unit comprises a first transistor, a second transistor, a first control transistor, a second control transistor, an input end and an output end. The detection circuit further comprises third transistors which are located between adjacent fundamental oscillation units. The fundamental oscillation units and the third transistors are connected in series to form an annular oscillator. According to the embodiment of the invention, the bias voltage temperature instability detection circuit can respectively detect the degree of threshold voltage degradation, which is caused by negative bias voltage temperature instability, of a PMOS transistor and the degree of threshold voltage degradation, which is caused by positive bias voltage temperature instability, of an NMOS transistor; by using the third transistors, the degree of threshold voltage degradation, which is caused by bias voltage temperature instability, of an MOS transistor can be amplified; and the final detection result is sensitive and the detection precision is high.

The invention relates to the technical field of integrated circuits and provides a threshold voltage degradation measuring circuit. The circuit comprises two MOS (Metal Oxide Semiconductor) tubes which are connected in series, wherein the first MOS tube is a detected tube; a grid electrode of the first MOS tube is connected with first direct-current voltage, a source electrode and a substrate of the first MOS tube are simultaneously connected with source electrode voltage, and a drain electrode of the first MOS tube is connected with an output end; a grid electrode and a drain electrode of the second MOS tube are simultaneously connected with second direct-current voltage, and a source electrode and a substrate of the second MOS tube are simultaneously connected with the output end. According to the scheme disclosed by the invention, the threshold voltage degradation measuring circuit with a simple structure is provided; the circuit only comprises the two MOS tubes which are connected in series and the threshold voltage degradation condition of the tube to be detected can be directly measured by only measuring the voltage change of the output end; and the circuit only relates to the obtaining of one physical amount and does not need to carry out secondary process and analysis, so that the technical scheme has the advantages of simple structure, convenience for operation, time-saving property, accurate and direct results and easiness in implementation.

Method for fabricating a semiconductor device, including the steps of providing a first conductive type semiconductor substrate having a cell region and a logic region defined thereon, forming a first insulating film, second conductive type polysilicon, and a second insulating film in succession on the semiconductor substrate, selectively removing the first insulating film, the polysilicon, and the second insulating film, to form a floating gate pattern at the cell region, elevating a temperature initially in a state O₂ gas is injected, maintaining a fix temperature, and dropping the temperature in a state N₂ gas is injected, to form a gate oxide film on a surface of the semiconductor substrate at the logic region, and forming a gate electrode pattern at each of the cell region and the logic region, whereby preventing a threshold voltage of a semiconductor device from dropping due to infiltration of impurities from doped polysilicon at the cell region to the active channel region.

The invention discloses an NBTI degradation model obtaining method based on nonuniform distribution interface traps. The method comprises the steps that 1, interface trap distributions in different zone of an MOS device are divided to obtain total distribution frame of the interface traps; 2, according to geometric construction, the interface trap distribution density in each zone is calculated, and the total density of the nonuniform distribution interface traps is obtained; 3, threshold voltage deviation caused by NBTI is obtained according to the deltaNIT total density, and an NBTI degradation model based on geometric construction analysis is obtained. The actual distribution situation of the interface traps produced by an NBTI effect is incorporated in the model, accordingly the total density of interface trap charges produced in the MOS device can be accurately calculated, thus a threshold voltage degradation model is obtained, few fitting parameters are required, the applicability is wide, and the model provides more accurate precision for device reliability.

Methods and systems for computing threshold voltage degradation of transistors in an array of memory cells are disclosed. In accordance with one method, a process that models an expected usage of the array is selected. In addition, a hardware processor can run the process to populate the array with data over time to simulate the expected usage of the array. The method further includes compiling data that detail different durations at which each of the memory cells in the array stores 1 or at which each of the memory cells in the array stores 0. For each separate grouping of memory cells that share a common duration of the different compiled durations, a threshold voltage degradation is determined for each transistor in the corresponding grouping of cells based on at least one biased temperature instability model.

The invention is concerned with a kind of MOS field-effect transistor. The breadth of the poly gate to MOS field-effect transistor adds in linearity from the someplace of the simple channel insulated area closed to both sides of breadth and the silicon area on boundary of silicon area. The invention is also concerned with the production method of MOS field-effect transistor. At first, define the geometry parameter of the shape change to this poly gate, according to the degree of anti-narrow channel effect and the general characteristic of MOS field-effect transistor. Then, change domain according to the decided geometry parameter. It adds the breadth of the poly gate on the rim of field-effect transistor in linearity, and this is equal to add the length of channel to parasitical transistor and reduces its leakage current to advance the threshold voltage of parasitical transistor. Then the result is to reduce the leakage current of main and advance its threshold voltage and solve the problem that the descendant of threshold voltage caused from the improvement of anti-narrow channel effect of MOS field-effect transistor.

The invention discloses a SiC power tube threshold voltage degradation model under temperature and voltage stress. The SiC power tube threshold voltage degradation model under temperature and voltagestress comprises the specific steps: firstly, establishing a single stress degradation model of SiC power MOSFET threshold voltage under temperature stress and voltage stress according to an Arrheniusmodel, an inverse power law model and a degradation time model; and then fusing the obtained two single-stress threshold voltage degradation models into a threshold voltage degradation model of the SiC power MOSFET under temperature and voltage coupling dual stress by using three radial basis neurons. According to the method, the single-stress physical degradation model of the threshold voltage of the SiC power MOSFET is combined with the radial basis neurons, and the threshold voltage degradation model with higher universality under the working condition of considering both temperature and voltage is established, so that the degradation trend of the SiC power MOSFET can be accurately evaluated.

Methods and systems for computing threshold voltage degradation of transistors in an array of memory cells are disclosed. In accordance with one method, a process that models an expected usage of the array is selected. In addition, a hardware processor can run the process to populate the array with data over time to simulate the expected usage of the array. The method further includes compiling data that detail different durations at which each of the memory cells in the array stores 1 or at which each of the memory cells in the array stores 0. For each separate grouping of memory cells that share a common duration of the different compiled durations, a threshold voltage degradation is determined for each transistor in the corresponding grouping of cells based on at least one biased temperature instability model.

The invention provides a manufacturing method of STI (shallow trench insulation). The method comprises the following steps: firstly growing an LO (lining oxide) on the surface of a shallow trench which is formed in a substrate through etching, and then carrying out primary boron element doping and secondary nitrogen element doping on the LO; forming a first barrier layer with boron ion concentration which is 1-2 orders of magnitude higher than a P well at the part, adjacent to the substrate region, of the LO; forming a second barrier layer above the first barrier layer; and finally, depositing silicon oxide in the shallow trench, carrying out CMP(chemical mechanical polishing) and STI annealing, thus forming the STI. The manufacturing method provided by the invention utilizes the second barrier layer to block boron ions in the first barrier layer so as to keep the concentration of the boron ions in the first barrier layer; the concentration of the boron ions in the first barrier layer is higher than the P well, in a follow-up P well annealing process, and the first barrier layer can be used for effectively preventing the boron ions in the P well from passing through the LO so as to diffuse into the STI; and the concentration of the boron ions injected into the P well is kept, and the performance of an NMOS (N-channel mental-oxide-semiconductor) device is prevented from being influenced by the degression of a threshold voltage caused by the reduction of the concentration of the boron ions.

The invention belongs to the technical field of display and discloses a thin film transistor, a preparation method thereof, an array substrate, a display panel and a display device. The thin film transistor comprises a substrate, as well as an active layer and a source-drain electrode which are sequentially stacked on the substrate; and the projection of a source electrode in the source-drain electrode on the substrate is overlapped with the projection of part of the edge of the active layer on the substrate. According to the thin film transistor, the illumination-receiving area of the activelayer is small, so that the generation of holes can be effectively reduced, the concentration of photon-generated carriers under an illumination condition is reduced, and therefore, the defect statessuch as hole capture probability increase and threshold voltage reduction, of the TFT working in a high-temperature illumination environment are avoided, and the performance of the TFT device in the high-temperature illumination environment is improved. When the thin film transistor is applied to the display panel, the working performance of the display product in a high-temperature environment can be improved, and the reliability of the display product is enhanced.

The invention provides a flash memory and an erasing method thereof, an electronic system and a computer storage medium. The flash memory adds a corresponding information bit for each storage block so as to indicate whether the storage block is erased or not before power failure, which memory block in a flash memory is performing erasing operation can be easily known through the information bits before power failure, and after the flash memory is powered on next time, whether the memory block in the flash memory is not erased before power failure or not can be checked by reading the information stored in the information bits corresponding to the memory block, and further reprogramming operation is performed on each storage block in the power-on process of the flash memory, so that the problems that the threshold voltage VT of some storage units is reduced and data reading of the storage units is failed due to erasing stress of erasing a certain storage block by block in the flash memory can be avoided.