45 results about "Threshold voltage degradation" patented technology

It is an object of the present invention to provide a device which can be easily manufactured and obtain a ground state of an arbitrary Ising model. A semiconductor device includes a first memory cell and a second memory cell that interacts with the first memory cell, in which storage content of the first memory cell and the second memory cell is stochastically inverted. The storage content is stochastically inverted by dropping threshold voltages of the first memory cell and the second memory cell. The threshold voltages of the first and second memory cells are dropping by controlling substrate biases, power voltages, or trip points of the first and second memory cells.

A voltage converting circuit has an output terminal for supplying an output current at an output voltage to a load. In response to a transient of the load, a current sinking circuit allows a current source to provide a sink current flowing from the output terminal of the voltage converting circuit into a ground potential. The sink current is finite and stable. When the output voltage decreases below a threshold voltage, the current sinking circuit allows the current source to keep providing the finite and stable sink current for an extension time, causing the output voltage to decrease from the threshold voltage to a regulated value.

There are provided a substrate including an oxide TFT having improved initial threshold voltage degradation characteristics included in a driving circuit of a liquid crystal display (LCD) device, a method for fabricating the same, and a driving circuit for an LCD device using the same. The substrate including an oxide thin film transistor (TFT) includes: a base substrate divided into a pixel region and a driving circuit region; and a plurality of TFTs formed on the base substrate, wherein an initial threshold voltage of at least one of the plurality of TFTs formed in the driving circuit region is positive-shifted to have a predetermined level.

The invention provides bias voltage temperature instability detection circuit and detection method. The bias voltage temperature instability detection circuit comprises an odd number of fundamental oscillation units. Each fundamental oscillation unit comprises a first transistor, a second transistor, a first control transistor, a second control transistor, an input end and an output end. The detection circuit further comprises third transistors which are located between adjacent fundamental oscillation units. The fundamental oscillation units and the third transistors are connected in series to form an annular oscillator. According to the embodiment of the invention, the bias voltage temperature instability detection circuit can respectively detect the degree of threshold voltage degradation, which is caused by negative bias voltage temperature instability, of a PMOS transistor and the degree of threshold voltage degradation, which is caused by positive bias voltage temperature instability, of an NMOS transistor; by using the third transistors, the degree of threshold voltage degradation, which is caused by bias voltage temperature instability, of an MOS transistor can be amplified; and the final detection result is sensitive and the detection precision is high.

The invention relates to the technical field of integrated circuits and provides a threshold voltage degradation measuring circuit. The circuit comprises two MOS (Metal Oxide Semiconductor) tubes which are connected in series, wherein the first MOS tube is a detected tube; a grid electrode of the first MOS tube is connected with first direct-current voltage, a source electrode and a substrate of the first MOS tube are simultaneously connected with source electrode voltage, and a drain electrode of the first MOS tube is connected with an output end; a grid electrode and a drain electrode of the second MOS tube are simultaneously connected with second direct-current voltage, and a source electrode and a substrate of the second MOS tube are simultaneously connected with the output end. According to the scheme disclosed by the invention, the threshold voltage degradation measuring circuit with a simple structure is provided; the circuit only comprises the two MOS tubes which are connected in series and the threshold voltage degradation condition of the tube to be detected can be directly measured by only measuring the voltage change of the output end; and the circuit only relates to the obtaining of one physical amount and does not need to carry out secondary process and analysis, so that the technical scheme has the advantages of simple structure, convenience for operation, time-saving property, accurate and direct results and easiness in implementation.

Method for fabricating a semiconductor device, including the steps of providing a first conductive type semiconductor substrate having a cell region and a logic region defined thereon, forming a first insulating film, second conductive type polysilicon, and a second insulating film in succession on the semiconductor substrate, selectively removing the first insulating film, the polysilicon, and the second insulating film, to form a floating gate pattern at the cell region, elevating a temperature initially in a state O2 gas is injected, maintaining a fix temperature, and dropping the temperature in a state N2 gas is injected, to form a gate oxide film on a surface of the semiconductor substrate at the logic region, and forming a gate electrode pattern at each of the cell region and the logic region, whereby preventing a threshold voltage of a semiconductor device from dropping due to infiltration of impurities from doped polysilicon at the cell region to the active channel region.

The invention discloses an NBTI degradation model obtaining method based on nonuniform distribution interface traps. The method comprises the steps that 1, interface trap distributions in different zone of an MOS device are divided to obtain total distribution frame of the interface traps; 2, according to geometric construction, the interface trap distribution density in each zone is calculated, and the total density of the nonuniform distribution interface traps is obtained; 3, threshold voltage deviation caused by NBTI is obtained according to the deltaNIT total density, and an NBTI degradation model based on geometric construction analysis is obtained. The actual distribution situation of the interface traps produced by an NBTI effect is incorporated in the model, accordingly the total density of interface trap charges produced in the MOS device can be accurately calculated, thus a threshold voltage degradation model is obtained, few fitting parameters are required, the applicability is wide, and the model provides more accurate precision for device reliability.

The invention discloses an accelerated degradation model of a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) under alternating gate drive, which takes gate negative bias voltage, junction temperature, multiple stresses of gate voltage rise time and switching times as inputs and threshold voltage variation as outputs, solves the problem of inaccurate threshold voltage drift prediction of the SiC MOSFET under alternating-current BTI (Bias Temperature Instability), and improves the prediction accuracy of the SiC MOSFET under alternating-current BTI. The method can be used for describing the SiC MOSFET threshold voltage degradation rule in the alternating gate drive mode. According to the invention, the change rule of key performance parameters in the long-term use process of the SiC MOSFET device can be reflected, and the method has important significance for accurately evaluating and optimizing and improving the use reliability of the device.

Methods and systems for computing threshold voltage degradation of transistors in an array of memory cells are disclosed. In accordance with one method, a process that models an expected usage of the array is selected. In addition, a hardware processor can run the process to populate the array with data over time to simulate the expected usage of the array. The method further includes compiling data that detail different durations at which each of the memory cells in the array stores 1 or at which each of the memory cells in the array stores 0. For each separate grouping of memory cells that share a common duration of the different compiled durations, a threshold voltage degradation is determined for each transistor in the corresponding grouping of cells based on at least one biased temperature instability model.

The invention is concerned with a kind of MOS field-effect transistor. The breadth of the poly gate to MOS field-effect transistor adds in linearity from the someplace of the simple channel insulated area closed to both sides of breadth and the silicon area on boundary of silicon area. The invention is also concerned with the production method of MOS field-effect transistor. At first, define the geometry parameter of the shape change to this poly gate, according to the degree of anti-narrow channel effect and the general characteristic of MOS field-effect transistor. Then, change domain according to the decided geometry parameter. It adds the breadth of the poly gate on the rim of field-effect transistor in linearity, and this is equal to add the length of channel to parasitical transistor and reduces its leakage current to advance the threshold voltage of parasitical transistor. Then the result is to reduce the leakage current of main and advance its threshold voltage and solve the problem that the descendant of threshold voltage caused from the improvement of anti-narrow channel effect of MOS field-effect transistor.

A GaN power switching device comprises a GaN transistor switch SW_MAIN has an integrated drain voltage sense circuit, which comprises GaN sense transistor SW_SEN and GaN sense resistor RSEN, which at turn-on form a resistive divider for sensing the drain voltage of SW_MAIN to provide a drain voltage sense output VDSEN. Fault detection logic circuitry of a driver circuit generates a fault signal FLT when VDSEN reaches or exceeds a reference voltage Vref, which triggers fast turn-off of the gate of SW_MAIN, e.g. within less than 100 ns of an overcurrent or short circuit condition. During turn-off, RSEN resets VDSEN to zero. For two stage turn-off, the driver circuit further comprises fast soft turn-off circuitry which is triggered first by the fault signal to pull-down the gate voltage to the threshold voltage, followed by a delay before full turn-off of the gate of SW_MAIN by the gate driver.

The invention discloses a SiC power tube threshold voltage degradation model under temperature and voltage stress. The SiC power tube threshold voltage degradation model under temperature and voltagestress comprises the specific steps: firstly, establishing a single stress degradation model of SiC power MOSFET threshold voltage under temperature stress and voltage stress according to an Arrheniusmodel, an inverse power law model and a degradation time model; and then fusing the obtained two single-stress threshold voltage degradation models into a threshold voltage degradation model of the SiC power MOSFET under temperature and voltage coupling dual stress by using three radial basis neurons. According to the method, the single-stress physical degradation model of the threshold voltage of the SiC power MOSFET is combined with the radial basis neurons, and the threshold voltage degradation model with higher universality under the working condition of considering both temperature and voltage is established, so that the degradation trend of the SiC power MOSFET can be accurately evaluated.

The invention particularly relates to an integrated circuit coupling failure analysis method based on a neural network. The method comprises the following steps: constructing a ring oscillator circuit; inputting a preset stress condition into a failure analysis model based on a neural network, and obtaining threshold voltage degradation amount prediction data output by the model; wherein the failure analysis model is used for predicting threshold voltage degradation of the PMOS device; the stress condition data is matched with the ring oscillator circuit; configuring the threshold voltage degradation amount prediction data to a grid electrode of a key transistor in a ring oscillator circuit, and obtaining corresponding circuit frequency degradation data; and performing data comparison on the circuit frequency degradation data and preset verification data to obtain a first data comparison result, and generating coupling failure analysis data based on the first data comparison result. According to the method, an analysis model for coupling failure of the NBTI and the HCD of the PMOS transistor is established, so that errors of data analysis are reduced, and the application range is widened.

The invention discloses a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) threshold voltage accelerated degradation model under time-varying junction temperature stress, which takes a device time-varying junction temperature stress sequence, a threshold voltage degradation rate sequence and a device working switching frequency as inputs and takes a device threshold voltage variation as an output. Compared with the defect that an existing SiC MOSFET accelerated degradation model which only considers constant junction temperature stress cannot be suitable for actual task working conditions with non-constant temperature stress characteristics, the influence of a preorder junction temperature stress sequence on subsequent degradation under variable junction temperature stress can be considered; the threshold voltage change rule of the device under the time-varying junction temperature task working condition can be described more accurately, and the method is of great significance in evaluating and optimizing the use reliability of the device.

The present invention provides a method of forming a semiconductor device. The method comprises the steps of: providing a substrate having a fin thereon; forming a dummy gate oxide layer at the side wall and the top portion of the fin; forming a protection layer on the dummy gate oxide layer; forming an isolation layer on the substrate, wherein the isolation layer is located on the protection layer and covers the side wall of the fin; performing ion doping for the fin after the isolation layer is formed; and removing the part of the isolation layer to form an isolation structure covering partof the side wall of the fin, wherein the isolation structure exposes part of the protection layer. The method of forming a semiconductor device forms the dummy gate oxide layer prior to ion doping toavoid the thermal effect in the process of forming the dummy gate oxide layer through thermal treatment, the thermal effect can allow the doped ions doped in the fin to be diffused, the diffusion of the doped ions can reduce the ion doping dosage in the fin to cause the threshold voltage drop and influence the device performance.

Methods and systems for computing threshold voltage degradation of transistors in an array of memory cells are disclosed. In accordance with one method, a process that models an expected usage of the array is selected. In addition, a hardware processor can run the process to populate the array with data over time to simulate the expected usage of the array. The method further includes compiling data that detail different durations at which each of the memory cells in the array stores 1 or at which each of the memory cells in the array stores 0. For each separate grouping of memory cells that share a common duration of the different compiled durations, a threshold voltage degradation is determined for each transistor in the corresponding grouping of cells based on at least one biased temperature instability model.

The invention discloses an NBTI effect simulation method and device for a double-interface gate oxide structure device, and the method comprises the steps: building an NBTI simulation model based on a three-dimensional model of the double-interface gate oxide structure device, and simulating the generation and recovery process of an interface trap, a body trap and an oxide layer pre-stored hole trap in the NBTI effect, obtaining threshold voltage degradation components induced by different traps; performing NBTI effect degradation stage analog simulation on the basis to extract a first electrical parameter change condition of the double-interface gate oxide structure device to obtain a first threshold voltage degradation component and a first transfer characteristic curve; and on the basis of the device state subjected to NBTI degradation simulation, NBTI effect recovery stage analog simulation is carried out to extract a second electrical parameter change condition of the double-interface gate oxide structure device, and a second threshold voltage degradation component and a second transfer characteristic curve are obtained, so that the complexity of the NBTI effect is accurately reflected.

The invention provides a method for forming an NMOS (N-channel Metal Oxide Semiconductor) transistor. The method comprises the following steps of: providing a substrate and a grid structure located on the substrate; taking the grid structure as a mask to carry out ion implantation on the substrate, and forming a source area and a drain area in the substrate at the both sides of the grid structure; forming a stopping layer on the exposed surfaces of the substrate and the grid structure; forming a stress layer on the stopping layer, wherein the stopping layer is used for preventing hydrogen elements used in the forming environment of the stress layer from entering the source area and the drain area; carrying out heat treatment on the source area and the drain area; and removing the stopping layer and the strain layer. According to the method disclosed by the invention, the compact stopping layer is formed on the surfaces of the substrate and the grid structure before the stress layer is formed, so as to prevent the hydrogen elements used in the forming environment of the stress layer from entering the source area / drain area in the substrate. Therefore, the problem of descending of threshold voltage, caused when the diffusion of doped ions in the source area / drain area is enhanced by the hydrogen elements, is solved, the reliability of the threshold voltage is improved, and the property reliability of the NMOS transistor is further improved.

The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes the following steps carried out in sequence: (1) a transistor structure forming step, (2) a shallow trench forming step, and (3) an electrical isolation structure forming step; the transistor manufacturing step includes the following operations: providing a substrate, forming a dual well region on the substrate, and manufacturing a transistor structure in the dual well region; the dual well region includes an adjacent first well region and a second well region, and before the shallow trench forming step, the first well region and the second well region always remain continuously connected; the shallow trench forming step includes the following operations: forming a shallow trench at the boundary between the first well region and the second well region; the electrical isolation structure forming step includes the following operations: depositing an isolation oxide on the surface of the dual well region to form a shallow trench isolation structure and an electrical isolation layer. By keeping the first well region and the second well region continuously connected, the diffusion of well ions in other regions of the first well region / second well region to the boundary between the first well region and the second well region is suppressed, and the region where the well ions are uniformly doped in the first well region and the second well region is broadened. Based on this, the effect of suppressing the threshold voltage drop of the semiconductor device is achieved. At the same time, the above operations are also beneficial to simplifying the manufacturing process of the semiconductor device.

The application discloses a TCAD-based NBTI effect recovery stage simulation method, and the implementation steps are as follows: generating a target device structure and defining a model in TCAD simulation software, performing degradation simulation on the target device, performing recovery simulation on the degraded target device, respectively calculating the average value of the charged state ratio of the ABDWT model at the channel region and the gate oxide layer interface of the degraded target device and the target device at different recovery time points, calculating the ratio of the charged state ratio at each recovery time point, and finally multiplying the threshold voltage degradation amount of the degraded target device to obtain the threshold voltage degradation amount at each recovery time point. The application has the advantages of being completely developed based on the TCAD simulation tool, being simple in operation and calculation, being capable of reflecting the real behavior of micro particles, and being small in data error.

The invention discloses a method for recovering the threshold voltage reduction of a MOSFET after irradiation. The method comprises the following steps: step 1, providing the MOSFET, wherein the MOSFET is irradiated; and step 2: applying a voltage of a certain value to the gate or the drain of the MOSFET for a period of time so that a part of electrons enter the oxide layer of the gate of the MOSFET and are recombined with the trapped holes. The voltage is applied to the gate or the drain of the irradiated MOSFET so that the electrons enter the oxide layer of the gate and are recombined with trapped holes, the threshold voltage of the device can be recovered and the problem of severe threshold voltage reduction of the MOSFET at high temperature can be alleviated.

The invention discloses a temperature interaction identification method for threshold voltage degradation of a silicon carbide power MOSFET, and belongs to the technical field of reliability identification of electronic components. The method aims at solving the problem that in the prior art, a temperature interaction analysis method for silicon carbide power MOSFET threshold voltage degradation does not exist. The method comprises the following steps: firstly, carrying out an accelerated degradation test to obtain threshold voltage degradation data for temperature interaction identification, and then eliminating measurement abnormal fluctuation and measurement errors; fitting each group of sample data with the temperatures of Ti and Tj in the constant-temperature accelerated degradation test and each group of sample data at the second stage of the two-stage temperature accelerated degradation test respectively; and then statistical test is performed on the degradation path data, and whether degradation is influenced by temperature interaction is judged according to a statistical test result. The method is used for identifying the temperature interaction of MOSFET threshold voltage degradation.

The invention provides a manufacturing method of STI (shallow trench insulation). The method comprises the following steps: firstly growing an LO (lining oxide) on the surface of a shallow trench which is formed in a substrate through etching, and then carrying out primary boron element doping and secondary nitrogen element doping on the LO; forming a first barrier layer with boron ion concentration which is 1-2 orders of magnitude higher than a P well at the part, adjacent to the substrate region, of the LO; forming a second barrier layer above the first barrier layer; and finally, depositing silicon oxide in the shallow trench, carrying out CMP(chemical mechanical polishing) and STI annealing, thus forming the STI. The manufacturing method provided by the invention utilizes the second barrier layer to block boron ions in the first barrier layer so as to keep the concentration of the boron ions in the first barrier layer; the concentration of the boron ions in the first barrier layer is higher than the P well, in a follow-up P well annealing process, and the first barrier layer can be used for effectively preventing the boron ions in the P well from passing through the LO so as to diffuse into the STI; and the concentration of the boron ions injected into the P well is kept, and the performance of an NMOS (N-channel mental-oxide-semiconductor) device is prevented from being influenced by the degression of a threshold voltage caused by the reduction of the concentration of the boron ions.

The invention discloses a manufacturing method of an NROM and a device thereof. The method comprises the following steps of: forming a source electrode and a drain electrode below a working surface of a semiconductor substrate; etching a chute on the semiconductor substrate between the source electrode and the drain electrode, and infusing silicon ion on the chute section of the semiconductor substrate so as to ensure non-crystallization of the semiconductor substrate on the surface of the chute; forming an ONO insulation layer on the surfaces of the semiconductor substrate, the source electrode and the drain electrode, wherein the ONO insulation layer is projected corresponding to the section of the chute and is inlayed in the chute of the semiconductor substrate; and forming a control grid on the surface of the ONO insulation layer between the source electrode and the drain electrode. Compared with the NROM device with reduced size in equal proportion, the NROM device during operation relatively lengthens the effective chute and solves all kinds of problems resulting from reducing the length of the chute, such as declination of the threshold voltage of the device, higher leakage current and interference generated between two locations.

The present invention provides a method of forming a semiconductor device. The method comprises the steps of: providing a substrate having a fin thereon; forming a dummy gate oxide layer at the side wall and the top portion of the fin; forming a protection layer on the dummy gate oxide layer; forming an isolation layer on the substrate, wherein the isolation layer is located on the protection layer and covers the side wall of the fin; performing ion doping for the fin after the isolation layer is formed; and removing the part of the isolation layer to form an isolation structure covering partof the side wall of the fin, wherein the isolation structure exposes part of the protection layer. The method of forming a semiconductor device forms the dummy gate oxide layer prior to ion doping toavoid the thermal effect in the process of forming the dummy gate oxide layer through thermal treatment, the thermal effect can allow the doped ions doped in the fin to be diffused, the diffusion of the doped ions can reduce the ion doping dosage in the fin to cause the threshold voltage drop and influence the device performance.

The invention discloses a method for manufacturing a MOS field effect transistor. In the double gate oxide etching step, only the medium-voltage thick gate oxide in the middle part of the silicon region of the low-voltage MOS tube is etched away, and the two ends in the width direction of the MOS tube are kept close to the From somewhere within the silicon region at the junction of the shallow trench isolation region and the silicon region to a medium voltage thick gate oxide at the junction of the shallow trench isolation region and the silicon region. The invention improves the threshold voltage of the total transistor of the low-voltage MOS field effect transistor by retaining the medium-voltage thick gate oxide at the edge of the silicon region of the low-voltage MOS transistor, and improves the problem of threshold voltage drop caused by the reverse narrow channel effect of the MOS field effect transistor.

The invention discloses an NBTI degradation model obtaining method based on nonuniform distribution interface traps. The method comprises the steps that 1, interface trap distributions in different zone of an MOS device are divided to obtain total distribution frame of the interface traps; 2, according to geometric construction, the interface trap distribution density in each zone is calculated, and the total density of the nonuniform distribution interface traps is obtained; 3, threshold voltage deviation caused by NBTI is obtained according to the deltaNIT total density, and an NBTI degradation model based on geometric construction analysis is obtained. The actual distribution situation of the interface traps produced by an NBTI effect is incorporated in the model, accordingly the total density of interface trap charges produced in the MOS device can be accurately calculated, thus a threshold voltage degradation model is obtained, few fitting parameters are required, the applicability is wide, and the model provides more accurate precision for device reliability.

A method for operating nonvolatile memory element includes exerting negative bias at gate electrode, utilizing-FN tunneling mechanism to make electron inject into electric charge storage layer from gate electrode of memory unit and via multiplayer tunneling dielectric structure for causing initial voltage-rise of memory unit, exerting a positive bias on gate electrode, utilizing + FN tunneling mechanism to make electric cavity inject into said electric charge layer from said gate electrode of memory unit and via said tunneling dielectric structure for causing initial voltage-drop of memory unit.