24 results about "Postsynapse" patented technology

The invention discloses a synaptic plastic mechanism bionic circuit based on a threshold symmetric memristor, and relates to the technical field of bionic circuits, the bionic circuit comprises a pre-synaptic neuron circuit, the threshold symmetric memristor and a post-synaptic neuron circuit; the bionic circuit is divided into an excitatory synaptic moldability mechanism circuit and an inhibitory synaptic moldability mechanism circuit according to a synaptic moldability mechanism; the design method of the circuit comprises the following steps: firstly, designing neuron waveforms before and after synapse, then traversing changes of memristive synapse conductance values at different time intervals to obtain a corresponding curve of the conductance changes and the time intervals, verifying the fitting degree of a biological synapse plastic mechanism curve and the curve, and if the fitting degree is low, determining that the biological synapse plastic mechanism curve is not matched with the curve. And if not, redesigning the pulse waveforms before and after synapse. The synaptic plasticity mechanism simulated by the bionic circuit provided by the invention and a biological synaptic STDP mechanism model have a small fitting error, the provided design method is higher in universality, circuit parameters can be adjusted according to different memristors, and different forms of biological synaptic plasticity mechanisms can be simulated.

The present application relates to a neural network circuit, comprising a plurality of neuron circuits and a plurality of electronic synapse circuits, wherein at least one of the electronic synapse circuits is configured to receive input and control signals from a presynaptic neuron circuit and receive a feedback signal from a postsynaptic neuron circuit; wherein the electronic synapse circuit comprises at least: a first transistor, a weight unit, a second transistor, a third transistor, and a fourth transistor; the present application also relates to an electronic device comprising the aforementioned neural network circuit.

The invention discloses synaptic circuits, a method, equipment and a medium for avoiding displacement current of a ferroelectric tunnel junction, and relates to the technical field of pulse neural networks, the synaptic circuits and the post-neuron circuit are of the same structure, the synaptic circuits are used for generating tunneling current when voltage difference exists at two ends of the ferroelectric tunnel junction, and the post-neuron circuit is used for generating the displacement current when voltage difference exists at two ends of the ferroelectric tunnel junction. An internal capacitor in the ferroelectric tunnel junction is controlled to discharge, the voltage in the synaptic circuit is raised, and a charging voltage is output when a pre-synaptic neuron pulse signal is received; the post neuron circuit is respectively connected with the plurality of synaptic circuits and is used for outputting post-synaptic neuron pulse signals according to the accessed charging voltage; and the synaptic circuit is also used for changing the voltage amplitude applied to the two ends of the ferroelectric tunnel junction according to the time interval between the received post-synaptic neuron pulse signal and the input signal, so that the reading error and the pulse neural network application bottleneck caused by the capacitance current characteristic and the resistance current characteristic of the ferroelectric tunnel junction are solved.

This invention relates to the field of neuromorphic computing technology and provides a method and system for dynamic adjustment of synaptic weights in real-time neurofeedback for neuromorphic chips. The method includes: capturing the pulse signals and timestamps emitted by presynaptic and postsynaptic neurons; calculating the time difference between the presynaptic and postsynaptic pulses; when the absolute value of the time difference is less than a preset time window threshold, querying a pulse timing dependency plasticity rule base based on the sign of the time difference to determine the corresponding synaptic weight adjustment type; generating corresponding voltage pulse parameters based on the adjustment type and the current conductance state of the target memristor synapse; and applying a write voltage pulse to the target memristor synapse according to the voltage pulse parameters to adjust its conductance value in situ in real time, thereby dynamically updating the synaptic weights. This invention solves the problems of poor dynamic environment adaptability, low energy efficiency, and high learning latency caused by traditional offline weight update mechanisms.

The application provides a brain-like synapse learning method and a brain-like technology neural morphological hardware system, and the method comprises the following steps: determining a pulse pair generated by a presynaptic neuron and a postsynaptic neuron in a brain-like synapse learning circuit, wherein the pulse pair comprises an input pulse generated by the presynaptic neuron and an output pulse generated by the postsynaptic neuron; determining an STDP mechanism corresponding to the pulse pair and a synapse weight corresponding to the STDP mechanism based on the pulse pair; and performing STDP learning corresponding to the brain-like synapse learning circuit based on the pulse pair and the synapse weight; wherein the STDP mechanism is a pulse time-dependent plasticity mechanism, and the front and rear pulses of the pulse pair correspond to a long-term potentiation process or a long-term depression process in the STDP mechanism according to the time sequence. The application realizes online learning of brain-like intelligence, and plays the environment self-adaptive characteristics of brain-like computing.

The present invention provides a multiomics approach, which integrate single-cell RNA-sequencing (scRNA-seq) and spatiotemporal transcriptomics (ST) offering potential for dissecting transcriptional networks and revealing cell-cell interactions involved in biomolecular pathomechanisms. The present invention also provides a multimodal approach combining high-throughput scRNA-seq and ST to elucidate XLRS-specific transcriptomic signatures in two XLRS-like models with retinal splitting phenotypes, including genetically engineered (Rs1emR209C) mice and patient-derived retinal organoids harboring the same patient-specific p.R209C mutation. Through multiomics transcriptomic analysis, the endoplasmic reticulum (ER) stress / eIF2 signaling, mTOR pathway, and the regulation of eIF4 and p70S6K pathways as chronically enriched and highly conserved disease pathways between two XLRS-like models are identified. Western blots and proteomics analysis validated the occurrence of unfolded protein responses, chronic eIF2α signaling activation, and chronic ER stress-induced apoptosis. Furthermore, therapeutic targeting of the chronic ER stress / eIF2α pathway activation synergistically enhanced the efficacy of AAV mediated RS1 gene delivery, ultimately improving bipolar cell integrity, postsynaptic transmission, disorganized retinal architecture and electrophysiological responses. Collectively, the complex transcriptomic signatures obtained from Rs1emR209C mice and patient-derived retinal organoids using the multiomics approach provide opportunities to unravel potential therapeutic targets for incurable retinal diseases, such as XLRS.

There is provided a neurosynaptic processing core with spike time dependent plasticity (STDP) learning for a spiking neural network, including: a spiking neuron block including a pre-synaptic block and a post-synaptic block; a synapse block communicatively coupled to the spiking neuron block; a STDP learning block communicatively coupled to the spiking neuron block and the synapse block, the STDP learning block including a pre-synaptic event accumulator including a pre-synaptic spike event memory block and a pre-synaptic spike parameter modifier; a post-synaptic event accumulator including a post-synaptic spike event memory block and a post-synaptic spike parameter modifier, a weight change accumulator, and a weight change parameter modifier; a learning error modulator; and a synaptic weight modifier configured to modify a synaptic weight parameter based on a weight change parameter and a learning error corresponding to the synaptic weight parameter. There is also provided a corresponding method of operating and a corresponding method of forming the neurosynaptic processing core.

A method (100) for distributed learning of a temporal neural network in a communication network. The method is performed by a first node of the communication network, the first node associated to a pre-synaptic neuron of the temporal neural network. The method comprises receiving (S101), from a second node of the communication system, the second node associated to a post-synaptic neuron of the temporal neural network, an indication that a hidden state of the post- synaptic neuron has changed. The method comprises transmitting (S102), to the second node, a pre-synaptic stimuli and receiving (S103), with a scheduled acknowledgement message associated to the transmitted pre-synaptic stimuli, a hidden state information related to the post-synaptic neuron. Further disclosed are related apparatuses, computer programs, and computer program products.

The application discloses a kind of video physiological signal dynamic extraction method and device, collect video and carry out face detection and posture correction to each frame video;The corrected face image is divided into micro-grid, and the brightness of each micro-grid is response-delay coding, and the pulse sequence of presynaptic pulse neuron is generated;Through membrane potential model and mutual inhibition between pulse neurons, competition is carried out and combined with connection weight, and the pulse emission time and pulse frequency of postsynaptic pulse neuron are obtained;According to the time difference between presynaptic and postsynaptic pulse neuron, dynamically adjust connection weight;After sorting and screening the pulse frequency of all postsynaptic neurons, it is mapped to the pulse sequence formed by corresponding micro-grid and weighted fusion, and the final pulse wave signal is generated;Finally, the physiological parameters of practitioner are obtained by calculating pulse wave signal, and the connection weight is adjusted by signal quality evaluation, and the strategy optimization of pulse wave signal extraction is realized continuously.

A method (100) for distributed learning of a temporal neural network in a communication network. The method is performed by a first node of the communication network, the first node associated to a pre-synaptic neuron of the temporal neural network. The method comprises receiving (S101), from a second node of the communication system, the second node associated to a post-synaptic neuron of the temporal neural network, an indication that a hidden state of the post- synaptic neuron has changed. The method comprises transmitting (S102), to the second node, a pre-synaptic stimuli and receiving (S103), with a scheduled acknowledgement message associated to the transmitted pre-synaptic stimuli, a hidden state information related to the post-synaptic neuron. Further disclosed are related apparatuses, computer programs, and computer program products.

A synapse surgical tool for selectively removing or ablating a postsynaptic terminal from a neuron, the method comprising: delivering an expression vector comprising a nucleic acid encoding a fusion protein comprising an N-terminal domain comprising an activated glial receptor binding domain; and a C terminal domain comprising a transmembrane domain of postsynaptic protein; expressing the fusion protein so that the activated glial receptor binding domain is localized to a synaptic cleft of the postsynaptic terminal of the neuron; and contacting the neuron with an activated microglial cell so that the activated microglial binds to the activated glial receptor binding domain and selectively ablates the postsynaptic terminal of the neuron.

A large-scale visual cortex neural network simulation method based on the concept of virtual synapses involves brain-like computing, neural network modeling and simulation. The synaptic conductance calculation strategy of "virtual synapses" is used to reduce the independence of the calculation process of each state variable, and the neuron parameter update is synchronized by multiple threads with the help of the CUDA computing platform. The synaptic conductance calculation strategy of "virtual synapses" is used. "Virtual synapses" are the integration of synaptic inputs received by postsynaptic neurons. Each postsynaptic neuron has n "virtual synapses". When simulating large-scale neural networks, the present invention reduces the huge synaptic current calculation process and reduces the independence of the calculation process of each state variable to save memory usage and reduce time consumption.

A neuromorphic device includes: a neuron block unit including a plurality of neurons; a synapse block unit including a plurality of synapses; and a topology block unit including a plurality of parallel Look-Up Table (LUT) modules including pre and post neuron elements configured with addresses of a presynaptic neuron and a postsynaptic neuron. Each of the plurality of neurons has an intrinsic address, each of the plurality of synapses has an intrinsic address. The parallel LUT module is partitioned based on a first synapse address among synapse addresses, and each of the partitions is indexed based on a second synapse address among the synapse addresses.

The application discloses a terahertz neural synapse memorization device and a preparation method thereof. The terahertz neural synapse memorization device comprises a substrate, an active region formed on the substrate, two electrodes in the form of interdigital electrodes, the two electrodes comprising test parts and finger parts, the test parts of the two electrodes being respectively formed on two sides of the active region, the finger parts being arranged on the active region in a staggered manner at a certain interval, and the interval between adjacent finger parts being controlled at a nanometer level; the two electrodes are respectively used as a presynaptic end and a postsynaptic end of a neural synapse, a high-frequency voltage signal is applied to the presynaptic end as an excitation source of the neural synapse, and a current signal response of the postsynaptic end is collected, so that a terahertz neural morphological calculation function is realized.

The invention discloses a memristor neural network circuit based on emotion influence STDP learning rate, which realizes biological synaptic plasticity through resistance plasticity and threshold value characteristics of a memristor, and simulates the regulation effect of emotion on brain learning rate. The circuit is composed of a pre-synaptic neuron, a post-synaptic neuron, a pulse module and a sensitive module. Wherein the pre-synaptic neurons and the post-synaptic neurons receive environment input signals and emotion signals, and the input mood signals are learned by using the weight adjustment module and the memristor; the pulse module compares a difference value between the neuron output signal and the emotion signal, and outputs a pulse signal when the difference value is lower than a threshold voltage; the sensitive module dynamically adjusts the resistance value of the memristor according to the pulse signal so as to simulate the emotion, thereby adjusting the weight and adjusting the voltage. When the emotion is excited, the learning rate is increased; when the emotion is low, the learning rate is reduced, and the circuit effectively simulates the influence of the emotion on the STDP learning rate.

A neuromorphic circuit (500) includes a crossbar synapse array unit. The crossbar synapse array unit includes a complementary metal oxide semiconductor (CMOS) transistor (T6), the on-resistance of which is controlled by the gate voltage of the CMOS transistor (T6) to update the weight of the crossbar synapse array unit. The neuromorphic circuit (500) also includes a set of row lines, each of which connects the synapse array unit in series with a plurality of presynaptic neurons at a first end of the synapse array unit. The neuromorphic circuit (500) also includes a set of column lines, each of which connects the synapse array unit in series with a plurality of postsynaptic neurons at a second end of the synapse array unit. The gate voltage of the CMOS transistor (T6) is controlled by performing a charge sharing technique, wherein the charge sharing technique uses non-overlapping pulses on a cell control line aligned with the set of row lines and the set of column lines to update the weight of the crossbar synapse array unit.

The present invention relates to the field of drug development and neuropharmacology. One aspect of this invention involves a method for screening substances that increase the stability of excitatory synaptic connections under destabilizing conditions. This method entails exposing a tested compound to an in vitro differentiated neuron culture along with a destabilization compound, followed by incubation with the test compound. Subsequently, a postsynaptic parameter is measured in the neurons, and this measurement is compared to that of neurons not exposed to the tested substance. This high-content screening system represents a significant advancement in neuropharmacology and drug discovery, offering automated and high-throughput capabilities for assessing the effects of chemical compounds on neuronal connections in vitro. Another aspect of the invention pertains to the use of dilazep, penbutolol, and their salts for alleviating and treating symptoms associated with depressive disorders.

The present invention relates to the field of drug development and neuropharmacology. One aspect of this invention involves a method for screening substances that increase the stability of excitatory synaptic connections under destabilizing conditions. This method entails exposing a tested compound to an in vitro differentiated neuron culture along with a destabilization compound, followed by incubation with the test compound. Subsequently, a postsynaptic parameter is measured in the neurons, and this measurement is compared to that of neurons not exposed to the tested substance. This high-content screening system represents a significant advancement in neuropharmacology and drug discovery, offering automated and high-throughput capabilities for assessing the effects of chemical compounds on neuronal connections in vitro. Another aspect of the invention pertains to the use of dilazep, penbutolol, and their salts for alleviating and treating symptoms associated with depressive disorders.

A synaptic circuit according to an embodiment is a circuit in which a weight value changed by learning is set. The synaptic circuit receives a binary input signal from a pre-synaptic neuron circuit and outputs an output signal to a post-synaptic neuron circuit. The synaptic circuit includes a propagation circuit and a control circuit. The propagation circuit supplies, to the post-synaptic neuron circuit, the output signal obtained by adding an influence of the weight value to the input signal. The control circuit stops output of the output signal from the propagation circuit to the post-synaptic neuron circuit when the weight value is smaller than a predetermined reference value.

The invention discloses a storage method for pulse target sharing of a neuron computer, which comprises the following steps: a neuron corresponds to an axon, a pulse target is finally converted into an axon tail end, a core axon data memory maintains an axon tail end list formed by continuously stored axon tail ends, the axon points to an initial address of the corresponding axon tail end list, and the axon tail end list corresponds to the initial address of the axon tail end list; when the neurons give out pulses, all the axon tail ends are traversed from the axon tail ends at the initial address of the axon tail end list to the high address direction in sequence, and the multiple axons can share the last multiple axon tail ends in the same axon tail end list. For the full connection layer of the spiking neural network, as each presynaptic neuron is connected to all post-synaptic neuron, each presynaptic neuron can share the same axon end list, so that the storage overhead is remarkably reduced. Updating is carried out according to the five types of axon states, and three types of axon updating requests are processed respectively.

The present invention discloses a neurosynaptic structure for a spiking neural network, wherein the neurosynaptic structure comprises: one or more input ports, one or more synaptic elements, each synaptic element connected to at least one of the input ports and configured to receive an input signal and to output a weighted postsynaptic signal. Furthermore, the neurosynaptic structure comprises a neuron connected to the one or more synaptic elements. The neurosynaptic structure is provided with different feedback and control structures such as AMPA-, GABA-, and NMDA receptors, axon-, dendrite- and neuron back-propagation channels and / or an astrocytes structure.

The invention relates to the technical field of neural networks, and discloses a spiking neural network acceleration method and device, equipment, a storage medium and a product, and the method comprises the steps: carrying out the descending sorting of pre-synaptic neurons according to the weight; gradually accumulating the weights of the activated pre-synaptic neurons into the membrane potential of the post-synaptic neurons according to the sorting sequence; in the step-by-step accumulation process, when the membrane potential of the post-synaptic neurons is larger than the excitation threshold potential, the post-synaptic neurons output pulses so as to improve the calculation efficiency.

The present invention belongs to the technical field of microprocessors, and specifically discloses a lightweight on-chip learning method based on a simplified SDSP algorithm for training spiking neural networks, including: performing rate encoding on an input image to convert a static frame image into a spiking form, and regarding each pixel point as a presynaptic neuron; the output layer of the spiking neural network consists of leaky integrate-and-fire neurons, where each neuron is a postsynaptic neuron, and the presynaptic neurons and the postsynaptic neurons are connected in a fully connected manner. Among them, the spikes emitted by the presynaptic neurons are presynaptic spikes, and the spikes emitted by the postsynaptic neurons are postsynaptic spikes; during the training of the spiking neural network, the weights of each synapse are updated according to a simplified spike-driven synaptic plasticity weight update method based on the calcium concentration Ca of the postsynaptic neuron. The present invention also discloses a system and a processor based on this method.

A method for processing data based on a neural network including a first layer including axons and a second layer including neurons, includes receiving synaptic weights between the first layer and the second layer; generating presynaptic weights, a number of which is identical to a number of the axons, and postsynaptic weights, a number of which is identical to a number of the synaptic weights, from the synaptic weights; and storing the presynaptic weights and the postsynaptic weights in a synapse memory.