2results about How to "Reduce sampling points" patented technology

This invention provides a path planning method belonging to the field of robot path planning, comprising: constructing a non-uniform dynamic partitioning strategy based on the obstacle distribution density within the workspace, prioritizing the selection of key areas that the path may traverse, and reducing the generation of redundant nodes and edges; constructing a weighted sampling strategy based on the comprehensive distance between sampling points and obstacles, increasing the sampling density of obstacle boundaries and narrow passage areas, and reducing invalid sampling in free space; constructing an adaptive variable step-size connection strategy based on the regional obstacle distribution characteristics, dynamically adjusting the node connection step size to enhance the connectivity of the route graph and reduce redundant edges; and performing path querying using a graph search algorithm based on the constructed probabilistic route graph, and performing cubic spline interpolation smoothing on the generated original path to obtain a smooth final path. This method is applicable to path planning in two-dimensional and three-dimensional spaces and for multi-degree-of-freedom robotic arms, and can effectively shorten path length and reduce planning time.

The application discloses a high-precision ADC linearity test method and system, comprising the following steps: inputting a plurality of signal differences to an ADC through a control signal generator, a voltage source, an operator and a channel of a multiplexer, and obtaining a group of output code bits of each signal difference; summing and subtracting two preset signal differences, and summing and subtracting the output code bits of the two preset signal differences, to obtain summing and subtracting results; determining a multivariate linear equation group according to a preset segmented nonlinear model containing a parameter to be solved, the summing and subtracting results and the output code bits; obtaining an optimal solution by solving the equation group, and determining integral nonlinear errors and differential nonlinear errors of the ADC according to the optimal solution and the preset segmented nonlinear model. The application can calculate common-mode and differential-mode of integral nonlinearity and differential nonlinearity, can reduce the precision requirement of an input signal, can greatly shorten test time and sampling points, and has simple system structure, fast algorithm running speed and wide application prospect.