74results about How to "Reduce write operations" patented technology

A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory cell. To this end, a voltage Vdd′ higher than a power supply voltage Vdd of a power supply line for peripheral circuits is supplied from a power supply line for memory cells as a power supply voltage for memory cells. Since the conductance of driver MOS transistors is increased, the threshold voltage of the MOS transistors within the memory cells can be reduced without reducing the static noise margin. Further the ratio of width between the driver MOS transistor and a transfer MOS transistor can be set to 1, thereby allowing a reduction in the memory cell area.

A static random access memory (SRAM) cell array is provided that reduces leakage current. The SRAM cell array is configured in a plurality of columns. Each of the columns comprises: a column virtual ground node; a column switch for selectively coupling the column virtual ground node to one of a ground or a nominal low voltage; and a plurality of segments. Each of the segments comprises: a segment virtual ground node; a plurality of SRAM cells including a virtual ground signal coupled to the segment virtual ground node; and a virtual ground switch for selectively coupling the segment virtual ground node to one of either a nominal low voltage or the column virtual ground node. A method for operating the SRAM cell array is also described.

The invention discloses a method and system of achieving data copying of solid-state hard disk FTL and a solid-state hard disk. The method comprises the steps of maintaining an address mapping list from a logical address LA to a physical address PA; maintaining an array or linked list of the physical address PAdest which becomes a destination of a copy, forming a reverse address mapping list from the mapping of the physical address PAdest to multiple logical address LAi, and maintaining the reverse address mapping list; receiving a copy-free copy command sent by a software to the solid-state hard disk, wherein the copy-free copy command includes a source logical address LAsrc of the copy, a destination logical address LAdest, and the number of data blocks which need to be copied; modifying the address mapping list and the reverse address mapping list based on a copy-free command, directing the destination logical address LAdest to the physical address to which the source logical address LAsrc is mapped, and completing the copy-free copying of the data. According to the method and system of achieving the data copying of solid-state hard disk FTL, unnecessary writing operations in the solid-state hard disk can be greatly reduced, the copying time is reduced, the service life of the solid-state hard disk is prolonged, and data reliability is improved.

A Y selection line for write for controlling operations of a column selection switch within a write amplifier and a Y selection line for read for controlling operations of a column selection switch within a read amplifier are provided individually and the column selection switch within the read amplifier is set to the non-operating condition during the write operation. Accordingly, a through-current during the write operation may be reduced. In this case, the write IO line and read IO line are allocated crossing sense amplifier columns, while the column selection line for write and column selection line for read are allocated in parallel to the sense amplifier columns.

The invention discloses a memory-based frequent pattern mining method. The method comprises the following steps of 1, creating an initial frequent pattern tree, creating a root node T of the frequent pattern tree, and marking the root node with ''null''; scanning a database again, selecting out frequent items in each read transaction, and sorting the frequent items according to an order in L; creating a path of the frequent pattern tree by taking null as the root node after sorting, adding 1 to a count of only a final node on the path, and keeping counts of other nodes on the path unchanged; scanning all transactions in the whole database in sequence and obtaining the initial frequent pattern tree; and 2, traversing the initial frequent pattern tree in sequence by using a depth-first search algorithm, wherein a counter value of a traversed node is the sum of the value of the node and the values of all child nodes of the node. The method has the technical effects that the write operation of an NVM (Non-Volatile Memory) can be reduced, so that the frequent pattern tree can be quickly established; and a large amount of dense write operations on a node counting domain close to the root node can be reduced, so that the service life of the NVM is prolonged.