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Method of polishing semiconductor wafers by using double-sided polisher

An object of the present invention is to provide a method of polishing semiconductor wafer by using a double-sided polisher which prevents a polish-sagging in an outer periphery of the wafer and thereby improves a degree of flatness of the semiconductor wafer. During polishing of the semiconductor wafer by using a double-sided polisher, a larger difference as compared to the prior art is created between a frictional resistance acting on a front surface of a silicon wafer W from an upper surface plate 12 side and a frictional resistance acting on a back surface of the silicon wafer W from a lower surface plate 13 side. This is because the present invention has employed a hard expanded urethane foam pad 14 and a soft non-woven fabric pad 15, which have different friction coefficients to the silicon wafer W from each other. Thereby, respective wafers W can be rotated at such a high speed as 0.1-1.0 rpm within corresponding wafer holding holes 11a. Accordingly, the rotation of the wafer would not be suspended even if there were any defective condition induced during polishing. Further, partial variation or deviation in polishing volume particular in the outer periphery of the wafer would be hard to occur. Therefore, the polish-sagging is suppressed and thus the improved degree of flatness of the wafer W could be obtained. Further, during this polishing, the semiconductor wafer is polished in a state in which a part of the outer periphery of the semiconductor wafer is protruded by 3-15 mm beyond said respective polishing cloths. During polishing, the outer periphery of the wafer is polished while passing through its non-polishing region at each time when the semiconductor wafer is rotated by a predetermined angle. Therefore, a contact area per unit time of the outer periphery of the wafer with the polishing cloths is reduced as compared to the central region of the wafer. As a result, the polish-sagging in the outer periphery of the wafer is suppressed and the degree of flatness of the wafer is improved.
Owner:SUMITOMO MITSUBISHI SILICON CORP
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