3 results about "Charge carrier injection" patented technology

According to the invention, an integrated circuit arrangement is formed by reducing the injection of charge carriers into a semiconductor substrate. The circuit arrangement comprises a first and second half-bridge connected as a full bridge, wherein the drain terminals of the first transistors and the source terminals of the second transistors are electrically connected. The two parallel-connected source terminals of the second transistors are connected to the first terminal of a two-terminal resistor, while the second terminal of the resistor provides a connection for a negative supply voltage or ground potential. A Zener diode is connected between the source terminal (supply voltage) and the gate terminal of at least one of the first MOS transistors. The transistors are surrounded by at least one guard ring.The guard ring is implemented as a contacted N or P well on the P or N substrate. Around the guard ring, further P or N wells, insulated by means of deep trench structures, are arranged.

An electrostatic discharge protection device is provided. The present device relates to a semiconductor device that is particularly suitable as a component for electrostatic discharge protection. The semiconductor device comprises a first structure, including: a third semiconductor region of the second charge type, a fourth semiconductor region of the first charge type and being spaced apart from the third semiconductor region, and a first connection element configured to electrically connect the third semiconductor region to the fourth semiconductor region. The third semiconductor region is arranged in between the first semiconductor region and the fourth semiconductor region, and the fourth semiconductor region is arranged in between the second semiconductor region and the third semiconductor region.

According to the invention, an integrated circuit arrangement is formed by reducing the injection of charge carriers into a semiconductor substrate. The circuit arrangement comprises a first and second half-bridge connected as a full bridge, wherein the drain terminals of the first transistors and the source terminals of the second transistors are electrically connected. The two parallel-connected source terminals of the second transistors are connected to the first terminal of a two-terminal resistor, while the second terminal of the resistor provides a connection for a negative supply voltage or ground potential. A Zener diode is connected between the source terminal (supply voltage) and the gate terminal of at least one of the first MOS transistors. The transistors are surrounded by at least one guard ring.The guard ring is implemented as a contacted N or P well on the P or N substrate. Around the guard ring, further P or N wells, insulated by means of deep trench structures, are arranged.