12 results about "Charge carrier injection" patented technology

The invention concerns an optoelectronic device comprising a hole injection channel with inclined sidewalls extending through the active layer and an underlying first n-doped layer, such that charge carriers from a second p-doped layer arranged above the active layer are injected both vertically and laterally into the underlying active layer. Improved mobility of holes and a resultant higher rate of recombination results in improved quantum efficiency. The dimensions and location of the hole injection channel are controllable, allowing greater uniformity of performance. A method of manufacturing such an optoelectronic device based on an epitaxial lateral overgrowth process and an optoelectronic arrangement comprising such optoelectronic devices are also disclosed.

According to the invention, an integrated circuit arrangement is formed by reducing the injection of charge carriers into a semiconductor substrate. The circuit arrangement comprises a first and second half-bridge connected as a full bridge, wherein the drain terminals of the first transistors and the source terminals of the second transistors are electrically connected. The two parallel-connected source terminals of the second transistors are connected to the first terminal of a two-terminal resistor, while the second terminal of the resistor provides a connection for a negative supply voltage or ground potential. A Zener diode is connected between the source terminal (supply voltage) and the gate terminal of at least one of the first MOS transistors. The transistors are surrounded by at least one guard ring.The guard ring is implemented as a contacted N or P well on the P or N substrate. Around the guard ring, further P or N wells, insulated by means of deep trench structures, are arranged.

An electrostatic discharge protection device is provided. The present device relates to a semiconductor device that is particularly suitable as a component for electrostatic discharge protection. The semiconductor device comprises a first structure, including: a third semiconductor region of the second charge type, a fourth semiconductor region of the first charge type and being spaced apart from the third semiconductor region, and a first connection element configured to electrically connect the third semiconductor region to the fourth semiconductor region. The third semiconductor region is arranged in between the first semiconductor region and the fourth semiconductor region, and the fourth semiconductor region is arranged in between the second semiconductor region and the third semiconductor region.

The invention concerns an optoelectronic device based on a p-type down configuration that achieves enhanced hole injection into the active region through a combination of lateral hole injection and alignment of polarization dipoles in the active region with the depletion field, allowing reduction of efficiency droop and achievement of lower forward bias. The alignment of the polarization field with the depletion field in the active region reduces the electrostatic barrier for electron and hole injection, compared to conventional p-up LEDs.

The invention concerns an optoelectronic device configured to achieve uniform charge carrier injection into the active region through a plurality of cavities with controllable position, dimensions, and distribution density. The plurality of cavities is formed through partial coalescence of lateral growth fronts in a facet controlled epitaxial lateral overgrowth (FACELO) process prior to device heterostructure deposition.

An organic light-emitting diode is provided. The organic light-emitting diode includes an anode, a cathode, and a light-emitting layer disposed therebetween. The cathode includes a ferromagnetic metal layer that selectively conducts spin-polarized electrons. An electron-conduction layer is disposed between the cathode and the light-emitting layer. A spin-polarizing hole-transport layer that supplies spin-polarized holes to the light-emitting layer is disposed between the anode and the light-emitting layer. The spin-polarized electrons and the spin-polarized holes recombine within the light-emitting layer.

It is an objective of the present disclosure to suppress charge carrier injection in a termination region, even in the event of a malfunction during back-gate operation, in a semiconductor device with a double-sided gate structure. A semiconductor device (101) with the double-sided gate structure comprises: a buffer layer (7) of a first conductivity type on a back face of a drift layer (9); and a collector layer (8) of a second conductivity type between the buffer layer (7) and a collector electrode (13) in an element region (31).A termination region (32) does not contain the collector layer (8) between the collector electrode (13) and the buffer layer (7), or the termination region (32) contains the collector layer (8) between the collector electrode (13) and the buffer layer (7) such that the collector layer (8) in the termination region (32) has a lower total amount of defects of the second conductivity type per unit area than the collector layer (8) in the element region (31).

According to the invention, an integrated circuit arrangement is formed by reducing the injection of charge carriers into a semiconductor substrate. The circuit arrangement comprises a first and second half-bridge connected as a full bridge, wherein the drain terminals of the first transistors and the source terminals of the second transistors are electrically connected. The two parallel-connected source terminals of the second transistors are connected to the first terminal of a two-terminal resistor, while the second terminal of the resistor provides a connection for a negative supply voltage or ground potential. A Zener diode is connected between the source terminal (supply voltage) and the gate terminal of at least one of the first MOS transistors. The transistors are surrounded by at least one guard ring.The guard ring is implemented as a contacted N or P well on the P or N substrate. Around the guard ring, further P or N wells, insulated by means of deep trench structures, are arranged.

The invention relates to an optoelectronic component (1) suitable for integration into an optoelectronic circuit, the component (1) comprising: - a III-V semiconductor membrane comprising: • a P-doped layer (2) called P layer; • an intrinsic layer (3) deposited on the P layer (2); and • an N-doped layer called N layer deposited on the intrinsic layer (3); - an asymmetric photonic-crystal waveguide (6, 16, 26) called PhC waveguide formed in the membrane by a two-dimensional photonic crystal on one longitudinal side and by a total internal reflection face on the other longitudinal side; - electrical contacts (10, 11) arranged respectively on either side of the PhC waveguide (6, 16, 26) in the plane of the membrane, suitable for injecting charge carriers laterally relative to the membrane into the PhC waveguide (6, 16, 26); the layers (2, 3, 4) being arranged so that the intrinsic layer and the N layer (3, 4) only partially cover the P layer (2), forming a lateral face (5) extending perpendicularly from the surface of the P layer (2), part of the lateral face (5) forming the total internal reflection face of the PhC waveguide; the PhC waveguide (6, 16, 26) being arranged to be evanescently coupled to a passive semiconductor waveguide (12) in at least one coupling region.

The embodiments of the present disclosure provide a light-emitting substrate, a method for producing the same, and a light-emitting device, relating to the field of display technology, and serve to solve the problem that residual layers formed by quantum dot phosphor materials can cause color mixing. A light-emitting substrate comprises a base substrate and several light-emitting components, each of which comprises a first electrode, a second electrode, and a light-emitting pattern. The several light-emitting components include at least one first light-emitting component, each of which comprises a first light-emitting pattern, a first charge carrier transport layer, and a first charge carrier injection layer.which are provided between the base substrate and the first light-emitting pattern, wherein the material of the first light-emitting pattern comprises a first cross-linked light-emitting material; the material of the first charge carrier transport layer comprises a first cross-linked charge carrier transport material; and the material of the first charge carrier injection layer comprises a first cross-linked charge carrier injection material. The above-mentioned light-emitting substrate is used in a light-emitting device.

This disclosure relates to a switching assembly using a bidirectional double-base bipolar junction transistor and a method of operating thereof. One example is a method comprising: injecting charge carriers into the upper base of the transistor at a first rate, the injection at the first rate causing a current to flow through the transistor from an upper collector-emitter to a lower collector-emitter, and the current flow causing a first voltage drop measured across the upper collector-emitter and the lower collector-emitter; and then, during a predetermined time period prior to the end of a first conduction cycle of the transistor, injecting charge carriers into the upper base at a second rate lower than the first rate, the injection at the second rate causing a second voltage drop measured across the upper collector-emitter and the lower collector-emitter, the second voltage drop being higher than the first voltage drop; and then deconducting the transistor at the end of the conduction cycle.