117 results about "Small magnitude" patented technology

The present invention relates to a method of transforming images, in particular photographs, into stereoscopic images, and also to images, and visual or audiovisual programs including sequences of images obtained by said method, and in particular to motion pictures and video games. The invention is achieved by:separating an image background into complementary color components, that are advantageously red, blue, and green;displacing at least one of the color components relative to the others, advantageously by shifting two color components through small amplitudes in opposite directions with the third color component, typically green, remaining stationary, or by rotating two color components in opposite directions through small amplitudes, with the third color component remaining stationary; andsuperposing an image that forms a foreground for the image.

Embodiments of the present invention enable compression and decompression of data. Applications of the present invention are its use in embodiments of systems for compression and decompression of GPS long-term Ephemeris (LTE) data, although the present invention is not limited to such applications. In embodiments, the LTE data may be grouped into a set of data values associated with a parameter. In embodiments, a data set may be compressed by using a multi-order differencing scheme. In such a scheme, a set of the differences between values may be compressed because the differences have smaller magnitudes than the values. In embodiments, a multi-order differencing scheme determines how many levels (orders) of differencing may be applied to an original data set before it is compressed. In embodiments, the original data may be recovered from a compressed data set based on the type of multi-order differencing scheme used to generate the compressed data.

A multiplicity of synchronized inverters for driving a multiplicity of loads such as CCFLs that require high ac voltages are arranged in close proximity of the respective loads and controlled in phase. A frequency determination capacitor and a frequency determination resistor are connected to one of the inverters to generate a triangular wave signal and a clock signal. The triangular wave signal and clock signal thus generated are supplied to other inverters to synchronize all the loads so that they can be controlled in phase. The resistance of the frequency determination resistor is set to a substantially small magnitude at the time of startup to increase the frequency of the triangular wave signal, thereby enabling quick startup of the loads.

Disclosed are a holographic reconstructing device and its application for portable electronic products. The holographic reconstructing device includes a compound hologram (9), a hologram seat (91), and a rebuilding light source (12). The compound hologram (9) is a flat-disk contour and disposed on the hologram seat (91). The rebuilding light source (12) is an LED and disposed under the hologram seat (91). The LED takes advantage of a small magnitude, less electricity consumption, simplified components, and a narrow bandwidth to definite a rebuilt image. The application of the flat-disk compound hologram is in a smooth-lying placement while reconstructing, which preferably occupies less space and facilitates user's observation as the rebuilt image is placed on the top of the compound hologram. The embedding of the holographic reconstructing device into the products would not affect the dimension of the products, thereby exhibiting realistic images on an individual space and forming a strong visual, clear impression, and a newly entertaining effect.

A family of logic circuits, called gated diode logic circuits, is disclosed wherein small amplitude signals, typically a fraction of the supply voltage, can be sensed and amplified by applying a small amplitude signal to a gate of a gated diode in a sampling mode and changing a voltage of a source of the gated diode in an evaluation mode. One or more isolation devices may be connected between each small amplitude signal and a gate of the gated diode, wherein the isolation device passes the small amplitude signal to the gate of the gated diode in the sampling mode, and isolates the small amplitude signal from the gate in the evaluation mode for amplification and performing fast logic operations (logic functions). The disclosed gated diode logic circuits overcome the Vt variation problem in FETs by detecting and amplifying the small logic signals utilizing gated diodes that have relatively low Vt variation. The amplified signals may then be processed by conventional logic circuits to perform certain logic functions in a gated diode logic circuit. The Vt variation of the gated diode is relatively small compared to the small logic signal amplitude and can be controlled relatively precisely. Typically, Vt of the gated diode can be set to a fraction of the small logic signal amplitude. Thus, in a gated diode logic circuit, the gated diode circuit can sense and amplify the small logic signals sufficiently to perform the various logic operations in conjunction with conventional logic circuits. The output(s) of the gated diode logic circuit can be of a standard full CMOS voltage swing, or can be scaled down in amplitude and further processed by other gated diode logic circuits.

A reference clock receiver structure according to the invention is provided. The structure preferably includes an input buffer that is formed from a PMOS differentiated pair of transistors and a first supply voltage. The PMOS differential pair receives a pair of differential inputs, and produces a pair of differential outputs. The structure also includes a level shifter that is coupled to receive the pair of differential outputs from the input buffer to provide gain to the pair of differential outputs to form a gained pair of differential outputs. The level shifter that includes a second supply voltage. The second supply voltage may have a smaller magnitude than the first supply voltage. Finally, the structure includes a CMOS buffer that is coupled to receive the gained pair of differential outputs. The CMOS buffer boosts the gained pair of differential outputs and converts the gained differential pair outputs into a single signal.