The invention relates to a chip simulation verification system. The system comprises a host side test module, a host side data conversion module, an instantiation docking module, a chip side data conversion module and a chip side test module. As verification personnel only need to realize an interface conversion function, namely, conversion from upper-layer data to hardware virtio protocol data is realized through the chip side data conversion module and the host side data conversion module, the verification personnel can be prevented from learning and knowing virtualization services of various projects, writing of heavy result comparison codes is avoided, and the verification efficiency is improved. According to the method and the system, simulation of a host side on an IO generation process is avoided, simulation on a whole virtio driver is avoided, errors possibly caused by designing rm and checker in a UVM architecture and rewriting heavy codes are avoided, then the workload of verification personnel can be greatly reduced, establishment of a verification platform is completed in a short time, and verification efficiency and verification quality are greatly improved.